Based on kernel version 6.11
. Page generated on 2024-09-24 08:21 EST
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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 | # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2 --- $id: http://devicetree.org/schemas/mtd/nand-controller.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: NAND Controller Common Properties maintainers: - Miquel Raynal <miquel.raynal@bootlin.com> - Richard Weinberger <richard@nod.at> description: | The NAND controller should be represented with its own DT node, and all NAND chips attached to this controller should be defined as children nodes of the NAND controller. This representation should be enforced even for simple controllers supporting only one chip. properties: $nodename: pattern: "^nand-controller(@.*)?" "#address-cells": const: 1 "#size-cells": const: 0 ranges: true cs-gpios: description: Array of chip-select available to the controller. The first entries are a 1:1 mapping of the available chip-select on the NAND controller (even if they are not used). As many additional chip-select as needed may follow and should be phandles of GPIO lines. 'reg' entries of the NAND chip subnodes become indexes of this array when this property is present. minItems: 1 maxItems: 8 patternProperties: "^nand@[a-f0-9]$": type: object $ref: raw-nand-chip.yaml# required: - "#address-cells" - "#size-cells" # This is a generic file other binding inherit from and extend additionalProperties: true examples: - | nand-controller { #address-cells = <1>; #size-cells = <0>; cs-gpios = <0>, <&gpioA 1>; /* A single native CS is available */ /* controller specific properties */ nand@0 { reg = <0>; /* Native CS */ /* NAND chip specific properties */ }; nand@1 { reg = <1>; /* GPIO CS */ }; }; |