Documentation / devicetree / bindings / memory-controllers / xlnx,versal-ddrmc-edac.yaml


Based on kernel version 6.9. Page generated on 2024-05-14 10:02 EST.

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/memory-controllers/xlnx,versal-ddrmc-edac.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Xilinx Versal DDRMC (Integrated DDR Memory Controller)

maintainers:
  - Shubhrajyoti Datta <shubhrajyoti.datta@amd.com>
  - Sai Krishna Potthuri <sai.krishna.potthuri@amd.com>

description:
  The integrated DDR Memory Controllers (DDRMCs) support both DDR4 and LPDDR4/
  4X memory interfaces. Versal DDR memory controller has an optional ECC support
  which correct single bit ECC errors and detect double bit ECC errors.

properties:
  compatible:
    const: xlnx,versal-ddrmc

  reg:
    items:
      - description: DDR Memory Controller registers
      - description: NOC registers corresponding to DDR Memory Controller

  reg-names:
    items:
      - const: base
      - const: noc

  interrupts:
    maxItems: 1

required:
  - compatible
  - reg
  - reg-names
  - interrupts

additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>
 
    bus {
      #address-cells = <2>;
      #size-cells = <2>;
      memory-controller@f6150000 {
        compatible = "xlnx,versal-ddrmc";
        reg = <0x0 0xf6150000 0x0 0x2000>, <0x0 0xf6070000 0x0 0x20000>;
        reg-names = "base", "noc";
        interrupt-parent = <&gic>;
        interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
      };
    };