Documentation / devicetree / bindings / memory-controllers / ti-aemif.txt


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* Device tree bindings for Texas instruments AEMIF controller

The Async External Memory Interface (EMIF16/AEMIF) controller is intended to
provide a glue-less interface to a variety of asynchronous memory devices like
ASRA M, NOR and NAND memory. A total of 256M bytes of any of these memories
can be accessed at any given time via four chip selects with 64M byte access
per chip select. Synchronous memories such as DDR1 SD RAM, SDR SDRAM
and Mobile SDR are not supported.

Documentation:
Davinci DM646x - http://www.ti.com/lit/ug/sprueq7c/sprueq7c.pdf
OMAP-L138 (DA850) - http://www.ti.com/lit/ug/spruh77a/spruh77a.pdf
Kestone - http://www.ti.com/lit/ug/sprugz3a/sprugz3a.pdf

Required properties:

- compatible:		"ti,davinci-aemif"
			"ti,keystone-aemif"
			"ti,da850-aemif"

- reg:			contains offset/length value for AEMIF control registers
			space.

- #address-cells:	Must be 2. The partition number has to be encoded in the
			first address cell and it may accept values 0..N-1
			(N - total number of partitions). It's recommended to
			assign N-1 number for the control partition. The second
			cell is the offset into the partition.

- #size-cells:		Must be set to 1.

- ranges:		Contains memory regions. There are two types of
			ranges/partitions:
			- CS-specific partition/range. If continuous, must be
			set up to reflect the memory layout for 4 chipselects,
			if not then additional range/partition can be added and
			child device can select the proper one.
			- control partition which is common for all CS
			interfaces.

- clocks:		the clock feeding the controller clock. Required only
			if clock tree data present in device tree.
			See clock-bindings.txt

- clock-names:		clock name. It has to be "aemif". Required only if clock
			tree data present in device tree, in another case don't
			use it.
			See clock-bindings.txt

- clock-ranges:		Empty property indicating that child nodes can inherit
			named clocks. Required only if clock tree data present
			in device tree.
			See clock-bindings.txt


Child chip-select (cs) nodes contain the memory devices nodes connected to
such as NOR (e.g. cfi-flash) and NAND (ti,davinci-nand, see davinci-nand.txt).
There might be board specific devices like FPGAs.

Required child cs node properties:

- #address-cells:	Must be 2.

- #size-cells:		Must be 1.

- ranges:		Empty property indicating that child nodes can inherit
			memory layout.

- clock-ranges:		Empty property indicating that child nodes can inherit
			named clocks. Required only if clock tree data present
			in device tree.

- ti,cs-chipselect:	number of chipselect. Indicates on the aemif driver
			which chipselect is used for accessing the memory. For
			compatibles "ti,davinci-aemif" and "ti,keystone-aemif"
			it can be in range [0-3]. For compatible
			"ti,da850-aemif" range is [2-5].

Optional child cs node properties:

- ti,cs-bus-width:		width of the asynchronous device's data bus
				8 or 16 if not preset 8

- ti,cs-select-strobe-mode:	enable/disable select strobe mode
				In select strobe mode chip select behaves as
				the strobe and is active only during the strobe
				period. If present then enable.

- ti,cs-extended-wait-mode:	enable/disable extended wait mode
				if set, the controller monitors the EMIFWAIT pin
				mapped to that chip select to determine if the
				device wants to extend the strobe period. If
				present then enable.

- ti,cs-min-turnaround-ns:	minimum turn around time, ns
				Time between the end of one asynchronous memory
				access and the start of another asynchronous
				memory access. This delay is not incurred
				between a read followed by read or a write
				followed by a write to same chip select.

- ti,cs-read-setup-ns:		read setup width, ns
				Time between the beginning of a memory cycle
				and the activation of read strobe.
				Minimum value is 1 (0 treated as 1).

- ti,cs-read-strobe-ns:		read strobe width, ns
				Time between the activation and deactivation of
				the read strobe.
				Minimum value is 1 (0 treated as 1).

- ti,cs-read-hold-ns:		read hold width, ns
				Time between the deactivation of the read
				strobe and the end of the cycle (which may be
				either an address change or the deactivation of
				the chip select signal.
				Minimum value is 1 (0 treated as 1).

- ti,cs-write-setup-ns:		write setup width, ns
				Time between the beginning of a memory cycle
				and the activation of write strobe.
				Minimum value is 1 (0 treated as 1).

- ti,cs-write-strobe-ns:	write strobe width, ns
				Time between the activation and deactivation of
				the write strobe.
				Minimum value is 1 (0 treated as 1).

- ti,cs-write-hold-ns:		write hold width, ns
				Time between the deactivation of the write
				strobe and the end of the cycle (which may be
				either an address change or the deactivation of
				the chip select signal.
				Minimum value is 1 (0 treated as 1).

If any of the above parameters are absent, current parameter value will be taken
from the corresponding HW reg.

Example for aemif, davinci nand and nor flash chip select shown below.

memory-controller@21000a00 {
	compatible = "ti,davinci-aemif";
	#address-cells = <2>;
	#size-cells = <1>;
	clocks = <&clkaemif 0>;
	clock-names = "aemif";
	clock-ranges;
	reg = <0x21000A00 0x00000100>;
	ranges = <0 0 0x70000000 0x10000000
		  1 0 0x21000A00 0x00000100>;
		  /*
		   * Partition0: CS-specific memory range which is
		   * implemented as continuous physical memory region
		   * Partition1: control memory range
		   */

	nand:cs2 {
		#address-cells = <2>;
		#size-cells = <1>;
		clock-ranges;
		ranges;

		ti,cs-chipselect = <2>;
		/* all timings in nanoseconds */
		ti,cs-min-turnaround-ns = <0>;
		ti,cs-read-hold-ns = <7>;
		ti,cs-read-strobe-ns = <42>;
		ti,cs-read-setup-ns = <14>;
		ti,cs-write-hold-ns = <7>;
		ti,cs-write-strobe-ns = <42>;
		ti,cs-write-setup-ns = <14>;

		nand@0,0x8000000 {
			compatible = "ti,davinci-nand";
			reg = <0 0x8000000 0x4000000
			       1 0x0000000 0x0000100>;
			/*
			 * Partition0, offset 0x8000000, size 0x4000000
			 * Partition1, offset 0x0000000, size 0x0000100
			 */

			.. see davinci-nand.txt
		};
	};

	nor:cs0 {
		#address-cells = <2>;
		#size-cells = <1>;
		clock-ranges;
		ranges;

		ti,cs-chipselect = <0>;
		/* all timings in nanoseconds */
		ti,cs-min-turnaround-ns = <0>;
		ti,cs-read-hold-ns = <8>;
		ti,cs-read-strobe-ns = <40>;
		ti,cs-read-setup-ns = <14>;
		ti,cs-write-hold-ns = <7>;
		ti,cs-write-strobe-ns = <40>;
		ti,cs-write-setup-ns = <14>;
		ti,cs-bus-width = <16>;

		flash@0,0x0000000 {
			compatible = "cfi-flash";
			reg = <0 0x0000000 0x4000000>;

			...
		};
	};
};