Documentation / devicetree / bindings / memory-controllers / calxeda-ddr-ctrlr.yaml


Based on kernel version 6.9. Page generated on 2024-05-14 10:02 EST.

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/memory-controllers/calxeda-ddr-ctrlr.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Calxeda DDR memory controller

description: |
  The Calxeda DDR memory controller is initialised and programmed by the
  firmware, but an OS might want to read its registers for error reporting
  purposes and to learn about the DRAM topology.

maintainers:
  - Andre Przywara <andre.przywara@arm.com>

properties:
  compatible:
    enum:
      - calxeda,hb-ddr-ctrl
      - calxeda,ecx-2000-ddr-ctrl

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

required:
  - compatible
  - reg
  - interrupts

additionalProperties: false

examples:
  - |
    memory-controller@fff00000 {
        compatible = "calxeda,hb-ddr-ctrl";
        reg = <0xfff00000 0x1000>;
        interrupts = <0 91 4>;
    };