Documentation / devicetree / bindings / memory-controllers / ti


Based on kernel version 6.9. Page generated on 2024-05-14 10:02 EST.

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* EMIF family of TI SDRAM controllers

EMIF - External Memory Interface - is an SDRAM controller used in
TI SoCs. EMIF supports, based on the IP revision, one or more of
DDR2/DDR3/LPDDR2 protocols. This binding describes a given instance
of the EMIF IP and memory parts attached to it. Certain revisions
of the EMIF controller also contain optional ECC support, which
corrects one bit errors and detects two bit errors.

Required properties:
- compatible	: Should be of the form "ti,emif-<ip-rev>" where <ip-rev>
  is the IP revision of the specific EMIF instance. For newer controllers,
  compatible should be one of the following:
  	     "ti,emif-am3352"
	     "ti,emif-am4372"
	     "ti,emif-dra7xx"
	     "ti,emif-keystone"

- phy-type	: <u32> indicating the DDR phy type. Following are the
  allowed values
  <1>	: Attila PHY
  <2>	: Intelli PHY

- device-handle	: phandle to a "lpddr2" node representing the memory part

- ti,hwmods	: For TI hwmods processing and omap device creation
  the value shall be "emif<n>" where <n> is the number of the EMIF
  instance with base 1.
- interrupts	: interrupt used by the controller

Required only for "ti,emif-am3352" and "ti,emif-am4372":
- sram			: Phandles for generic sram driver nodes,
  first should be type 'protect-exec' for the driver to use to copy
  and run PM functions, second should be regular pool to be used for
  data region for code. See Documentation/devicetree/bindings/sram/sram.yaml
  for more details.

Optional properties:
- cs1-used		: Have this property if CS1 of this EMIF
  instance has a memory part attached to it. If there is a memory
  part attached to CS1, it should be the same type as the one on CS0,
  so there is no need to give the details of this memory part.

- cal-resistor-per-cs	: Have this property if the board has one
  calibration resistor per chip-select.

- hw-caps-read-idle-ctrl: Have this property if the controller
  supports read idle window programming

- hw-caps-dll-calib-ctrl: Have this property if the controller
  supports dll calibration control

- hw-caps-ll-interface	: Have this property if the controller
  has a low latency interface and corresponding interrupt events

- hw-caps-temp-alert	: Have this property if the controller
  has capability for generating SDRAM temperature alerts

-Examples:

emif1: emif@4c000000 {
	compatible	= "ti,emif-4d";
	ti,hwmods	= "emif2";
	phy-type	= <1>;
	device-handle	= <&elpida_ECB240ABACN>;
	cs1-used;
	hw-caps-read-idle-ctrl;
	hw-caps-ll-interface;
	hw-caps-temp-alert;
};

/* From am33xx.dtsi */
emif: emif@4c000000 {
        compatible = "ti,emif-am3352";
        reg =   <0x4C000000 0x1000>;
        sram = <&pm_sram_code
                &pm_sram_data>;
};

emif1: emif@4c000000 {
	compatible = "ti,emif-dra7xx";
	reg = <0x4c000000 0x200>;
	interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
};