Documentation / devicetree / bindings / memory-controllers / qca,ath79-ddr-controller.yaml


Based on kernel version 6.9. Page generated on 2024-05-14 10:02 EST.

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/memory-controllers/qca,ath79-ddr-controller.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm Atheros AR7xxx/AR9xxx DDR controller

maintainers:
  - Krzysztof Kozlowski <krzk@kernel.org>

description: |
  The DDR controller of the AR7xxx and AR9xxx families provides an interface to
  flush the FIFO between various devices and the DDR. This is mainly used by
  the IRQ controller to flush the FIFO before running the interrupt handler of
  such devices.

properties:
  compatible:
    oneOf:
      - items:
          - const: qca,ar9132-ddr-controller
          - const: qca,ar7240-ddr-controller
      - items:
          - enum:
              - qca,ar7100-ddr-controller
              - qca,ar7240-ddr-controller
 
  "#qca,ddr-wb-channel-cells":
    description: |
      Specifies the number of cells needed to encode the write buffer channel
      index.
    $ref: /schemas/types.yaml#/definitions/uint32
    const: 1

  reg:
    maxItems: 1

required:
  - compatible
  - "#qca,ddr-wb-channel-cells"
  - reg

additionalProperties: false

examples:
  - |
    ddr_ctrl: memory-controller@18000000 {
        compatible = "qca,ar9132-ddr-controller",
                     "qca,ar7240-ddr-controller";
        reg = <0x18000000 0x100>;
 
        #qca,ddr-wb-channel-cells = <1>;
    };
 
    interrupt-controller {
        // ...
        qca,ddr-wb-channel-interrupts = <2>, <3>, <4>, <5>;
        qca,ddr-wb-channels = <&ddr_ctrl 3>, <&ddr_ctrl 2>,
                              <&ddr_ctrl 0>, <&ddr_ctrl 1>;
    };