Documentation / devicetree / bindings / memory-controllers / brcm,brcmstb-memc-ddr.yaml


Based on kernel version 6.9. Page generated on 2024-05-14 10:02 EST.

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/memory-controllers/brcm,brcmstb-memc-ddr.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Memory controller (MEMC) for Broadcom STB

maintainers:
  - Florian Fainelli <f.fainelli@gmail.com>

properties:
  compatible:
    items:
      - enum:
          - brcm,brcmstb-memc-ddr-rev-b.1.x
          - brcm,brcmstb-memc-ddr-rev-b.2.0
          - brcm,brcmstb-memc-ddr-rev-b.2.1
          - brcm,brcmstb-memc-ddr-rev-b.2.2
          - brcm,brcmstb-memc-ddr-rev-b.2.3
          - brcm,brcmstb-memc-ddr-rev-b.2.5
          - brcm,brcmstb-memc-ddr-rev-b.2.6
          - brcm,brcmstb-memc-ddr-rev-b.2.7
          - brcm,brcmstb-memc-ddr-rev-b.2.8
          - brcm,brcmstb-memc-ddr-rev-b.3.0
          - brcm,brcmstb-memc-ddr-rev-b.3.1
          - brcm,brcmstb-memc-ddr-rev-c.1.0
          - brcm,brcmstb-memc-ddr-rev-c.1.1
          - brcm,brcmstb-memc-ddr-rev-c.1.2
          - brcm,brcmstb-memc-ddr-rev-c.1.3
          - brcm,brcmstb-memc-ddr-rev-c.1.4
      - const: brcm,brcmstb-memc-ddr

  reg:
    maxItems: 1

  clock-frequency:
    description: DDR PHY frequency in Hz

required:
  - compatible
  - reg

additionalProperties: false

examples:
  - |
    memory-controller@9902000 {
        compatible = "brcm,brcmstb-memc-ddr-rev-c.1.1", "brcm,brcmstb-memc-ddr";
        reg = <0x9902000 0x600>;
        clock-frequency = <2133000000>;
    };