Based on kernel version 7.0. Page generated on 2026-04-23 09:48 EST.
| 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 | # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) %YAML 1.2 --- $id: http://devicetree.org/schemas/iio/adc/nxp,s32g2-sar-adc.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: NXP Successive Approximation ADC description: The NXP SAR ADC provides fast and accurate analog-to-digital conversion using the Successive Approximation Register (SAR) method. It has 12-bit resolution with 8 input channels. Conversions can be launched in software or using hardware triggers. It supports continuous and one-shot modes with separate registers. maintainers: - Daniel Lezcano <daniel.lezcano@kernel.org> properties: compatible: oneOf: - const: nxp,s32g2-sar-adc - items: - const: nxp,s32g3-sar-adc - const: nxp,s32g2-sar-adc reg: maxItems: 1 interrupts: maxItems: 1 clocks: maxItems: 1 dmas: maxItems: 1 dma-names: const: rx required: - compatible - reg - interrupts - clocks - dmas - dma-names additionalProperties: false examples: - | #include <dt-bindings/interrupt-controller/arm-gic.h> adc@401f8000 { compatible = "nxp,s32g2-sar-adc"; reg = <0x401f8000 0x1000>; interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks 0x41>; dmas = <&edma0 0 32>; dma-names = "rx"; }; |