Based on kernel version 6.19. Page generated on 2026-02-12 08:37 EST.
| 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 | # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2 --- $id: http://devicetree.org/schemas/ata/eswin,eic7700-ahci.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: Eswin EIC7700 SoC SATA Controller maintainers: - Yulin Lu <luyulin@eswincomputing.com> - Huan He <hehuan1@eswincomputing.com> description: AHCI SATA controller embedded into the EIC7700 SoC is based on the DWC AHCI SATA v5.00a IP core. select: properties: compatible: const: eswin,eic7700-ahci required: - compatible allOf: - $ref: snps,dwc-ahci-common.yaml# properties: compatible: items: - const: eswin,eic7700-ahci - const: snps,dwc-ahci clocks: minItems: 2 maxItems: 2 clock-names: items: - const: pclk - const: aclk resets: maxItems: 1 reset-names: const: arst ports-implemented: const: 1 required: - compatible - reg - interrupts - clocks - clock-names - resets - reset-names - phys - phy-names - ports-implemented unevaluatedProperties: false examples: - | sata@50420000 { compatible = "eswin,eic7700-ahci", "snps,dwc-ahci"; reg = <0x50420000 0x10000>; interrupt-parent = <&plic>; interrupts = <58>; clocks = <&clock 171>, <&clock 186>; clock-names = "pclk", "aclk"; phys = <&sata_phy>; phy-names = "sata-phy"; ports-implemented = <0x1>; resets = <&reset 96>; reset-names = "arst"; }; |