Based on kernel version 6.13
. Page generated on 2025-01-21 08:21 EST
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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 | # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause %YAML 1.2 --- $id: http://devicetree.org/schemas/timer/actions,owl-timer.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: Actions Semi Owl timer maintainers: - Andreas Färber <afaerber@suse.de> description: Actions Semi Owl SoCs provide 32bit and 2Hz timers. The 32bit timers support dynamic irq, as well as one-shot mode. properties: compatible: enum: - actions,s500-timer - actions,s700-timer - actions,s900-timer clocks: maxItems: 1 interrupts: minItems: 1 maxItems: 6 interrupt-names: minItems: 1 maxItems: 6 items: enum: - 2hz0 - 2hz1 - timer0 - timer1 - timer2 - timer3 reg: maxItems: 1 required: - compatible - clocks - interrupts - interrupt-names - reg allOf: - if: properties: compatible: contains: enum: - actions,s500-timer then: properties: interrupts: minItems: 4 maxItems: 4 interrupt-names: items: - const: 2hz0 - const: 2hz1 - const: timer0 - const: timer1 - if: properties: compatible: contains: enum: - actions,s700-timer - actions,s900-timer then: properties: interrupts: minItems: 1 maxItems: 1 interrupt-names: items: - const: timer1 additionalProperties: false examples: - | #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/interrupt-controller/irq.h> soc { #address-cells = <1>; #size-cells = <1>; timer@b0168000 { compatible = "actions,s500-timer"; reg = <0xb0168000 0x100>; clocks = <&hosc>; interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "2hz0", "2hz1", "timer0", "timer1"; }; }; ... |