Documentation / devicetree / bindings / timer / nvidia,tegra186-timer.yaml


Based on kernel version 6.11. Page generated on 2024-09-24 08:21 EST.

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/timer/nvidia,tegra186-timer.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: NVIDIA Tegra186 timer

maintainers:
  - Thierry Reding <treding@nvidia.com>

description: >
  The Tegra timer provides 29-bit timer counters and a 32-bit timestamp
  counter. Each NV timer selects its timing reference signal from the 1 MHz
  reference generated by USEC, TSC or either clk_m or OSC. Each TMR can be
  programmed to generate one-shot, periodic, or watchdog interrupts.
 

properties:
  compatible:
    oneOf:
      - const: nvidia,tegra186-timer
        description: >
          The Tegra186 timer provides ten 29-bit timer counters.
      - const: nvidia,tegra234-timer
        description: >
          The Tegra234 timer provides sixteen 29-bit timer counters.

  reg:
    maxItems: 1

  interrupts: true

allOf:
  - if:
      properties:
        compatible:
          contains:
            const: nvidia,tegra186-timer
    then:
      properties:
        interrupts:
          maxItems: 10
          description: >
            One per each timer channels 0 through 9.

  - if:
      properties:
        compatible:
          contains:
            const: nvidia,tegra234-timer
    then:
      properties:
        interrupts:
          maxItems: 16
          description: >
            One per each timer channels 0 through 15.

required:
  - compatible
  - reg
  - interrupts

additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/interrupt-controller/irq.h>
 
    timer@3010000 {
        compatible = "nvidia,tegra186-timer";
        reg = <0x03010000 0x000e0000>;
        interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
    };

  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/interrupt-controller/irq.h>
 
    timer@2080000 {
        compatible = "nvidia,tegra234-timer";
        reg = <0x02080000 0x00121000>;
        interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
    };