# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/remoteproc/qcom,sc7280-wpss-pil.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm SC7280 WPSS Peripheral Image Loader

maintainers:
  - Bjorn Andersson <bjorn.andersson@linaro.org>

description:
  This document defines the binding for a component that loads and boots firmware
  on the Qualcomm Technology Inc. WPSS.

properties:
  compatible:
    enum:
      - qcom,sc7280-wpss-pil

  reg:
    maxItems: 1
    description:
      The base address and size of the qdsp6ss register

  interrupts:
    items:
      - description: Watchdog interrupt
      - description: Fatal interrupt
      - description: Ready interrupt
      - description: Handover interrupt
      - description: Stop acknowledge interrupt
      - description: Shutdown acknowledge interrupt

  interrupt-names:
    items:
      - const: wdog
      - const: fatal
      - const: ready
      - const: handover
      - const: stop-ack
      - const: shutdown-ack

  clocks:
    items:
      - description: GCC WPSS AHB BDG Master clock
      - description: GCC WPSS AHB clock
      - description: GCC WPSS RSCP clock
      - description: XO clock

  clock-names:
    items:
      - const: ahb_bdg
      - const: ahb
      - const: rscp
      - const: xo

  power-domains:
    items:
      - description: CX power domain
      - description: MX power domain

  power-domain-names:
    items:
      - const: cx
      - const: mx

  resets:
    items:
      - description: AOSS restart
      - description: PDC SYNC

  reset-names:
    items:
      - const: restart
      - const: pdc_sync

  memory-region:
    maxItems: 1
    description: Reference to the reserved-memory for the Hexagon core

  firmware-name:
    maxItems: 1
    description:
      The name of the firmware which should be loaded for this remote
      processor.

  qcom,halt-regs:
    $ref: /schemas/types.yaml#/definitions/phandle-array
    description:
      Phandle reference to a syscon representing TCSR followed by the
      offset within syscon for q6 halt register.
    items:
      - items:
          - description: phandle to TCSR syscon region
          - description: offset to the Q6 halt register

  qcom,qmp:
    $ref: /schemas/types.yaml#/definitions/phandle
    description: Reference to the AOSS side-channel message RAM.

  qcom,smem-states:
    $ref: /schemas/types.yaml#/definitions/phandle-array
    description: States used by the AP to signal the Hexagon core
    items:
      - description: Stop the modem

  qcom,smem-state-names:
    description: The names of the state bits used for SMP2P output
    const: stop

  glink-edge:
    $ref: qcom,glink-edge.yaml#
    unevaluatedProperties: false
    description:
      Qualcomm G-Link subnode which represents communication edge, channels
      and devices related to the ADSP.

    properties:
      interrupts:
        items:
          - description: IRQ from WPSS to GLINK

      mboxes:
        items:
          - description: Mailbox for communication between APPS and WPSS

      label:
        items:
          - const: wpss

      apr: false
      fastrpc: false

required:
  - compatible
  - reg
  - interrupts
  - interrupt-names
  - clocks
  - clock-names
  - power-domains
  - power-domain-names
  - resets
  - reset-names
  - qcom,halt-regs
  - memory-region
  - qcom,qmp
  - qcom,smem-states
  - qcom,smem-state-names
  - glink-edge

additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/clock/qcom,gcc-sc7280.h>
    #include <dt-bindings/clock/qcom,rpmh.h>
    #include <dt-bindings/power/qcom-rpmpd.h>
    #include <dt-bindings/reset/qcom,sdm845-aoss.h>
    #include <dt-bindings/reset/qcom,sdm845-pdc.h>
    #include <dt-bindings/mailbox/qcom-ipcc.h>
    remoteproc@8a00000 {
        compatible = "qcom,sc7280-wpss-pil";
        reg = <0x08a00000 0x10000>;
 
        interrupts-extended = <&intc GIC_SPI 587 IRQ_TYPE_EDGE_RISING>,
                              <&wpss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
                              <&wpss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
                              <&wpss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
                              <&wpss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
                              <&wpss_smp2p_in 7 IRQ_TYPE_EDGE_RISING>;
        interrupt-names = "wdog", "fatal", "ready", "handover",
                          "stop-ack", "shutdown-ack";
 
        clocks = <&gcc GCC_WPSS_AHB_BDG_MST_CLK>,
                 <&gcc GCC_WPSS_AHB_CLK>,
                 <&gcc GCC_WPSS_RSCP_CLK>,
                 <&rpmhcc RPMH_CXO_CLK>;
        clock-names = "ahb_bdg", "ahb",
                      "rscp", "xo";
 
        power-domains = <&rpmhpd SC7280_CX>,
                        <&rpmhpd SC7280_MX>;
        power-domain-names = "cx", "mx";
 
        memory-region = <&wpss_mem>;
 
        qcom,qmp = <&aoss_qmp>;
 
        qcom,smem-states = <&wpss_smp2p_out 0>;
        qcom,smem-state-names = "stop";
 
        resets = <&aoss_reset AOSS_CC_WCSS_RESTART>,
                 <&pdc_reset PDC_WPSS_SYNC_RESET>;
        reset-names = "restart", "pdc_sync";
 
        qcom,halt-regs = <&tcsr_mutex 0x37000>;
 
        glink-edge {
            interrupts-extended = <&ipcc IPCC_CLIENT_WPSS
                                         IPCC_MPROC_SIGNAL_GLINK_QMP
                                         IRQ_TYPE_EDGE_RISING>;
            mboxes = <&ipcc IPCC_CLIENT_WPSS
                            IPCC_MPROC_SIGNAL_GLINK_QMP>;
 
            label = "wpss";
            qcom,remote-pid = <13>;
        };
    };