Based on kernel version 6.11
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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 | # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause %YAML 1.2 --- $id: http://devicetree.org/schemas/dma/socionext,uniphier-mio-dmac.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: UniPhier Media IO DMA controller description: | This works as an external DMA engine for SD/eMMC controllers etc. found in UniPhier LD4, Pro4, sLD8 SoCs. maintainers: - Masahiro Yamada <yamada.masahiro@socionext.com> allOf: - $ref: dma-controller.yaml# properties: compatible: const: socionext,uniphier-mio-dmac reg: maxItems: 1 interrupts: description: | A list of interrupt specifiers associated with the DMA channels. The number of interrupt lines is SoC-dependent. clocks: maxItems: 1 resets: maxItems: 1 '#dma-cells': description: The single cell represents the channel index. const: 1 required: - compatible - reg - interrupts - clocks - '#dma-cells' additionalProperties: false examples: - | // In the example below, "interrupts = <0 68 4>, <0 68 4>, ..." is not a // typo. The first two channels share a single interrupt line. dmac: dma-controller@5a000000 { compatible = "socionext,uniphier-mio-dmac"; reg = <0x5a000000 0x1000>; interrupts = <0 68 4>, <0 68 4>, <0 69 4>, <0 70 4>, <0 71 4>, <0 72 4>, <0 73 4>, <0 74 4>; clocks = <&mio_clk 7>; resets = <&mio_rst 7>; #dma-cells = <1>; }; |