Based on kernel version 6.11
. Page generated on 2024-09-24 08:21 EST
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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 | # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2 --- $id: http://devicetree.org/schemas/dma/arm-pl08x.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: ARM PrimeCells PL080 and PL081 and derivatives DMA controller maintainers: - Vinod Koul <vkoul@kernel.org> allOf: - $ref: /schemas/arm/primecell.yaml# - $ref: dma-controller.yaml# # We need a select here so we don't match all nodes with 'arm,primecell' select: properties: compatible: contains: enum: - arm,pl080 - arm,pl081 required: - compatible properties: compatible: oneOf: - items: - enum: - arm,pl080 - arm,pl081 - const: arm,primecell - items: - const: faraday,ftdma020 - const: arm,pl080 - const: arm,primecell reg: maxItems: 1 description: Address range of the PL08x registers interrupts: minItems: 1 description: The PL08x interrupt number clocks: minItems: 1 description: The clock running the IP core clock clock-names: maxItems: 1 lli-bus-interface-ahb1: type: boolean description: if AHB master 1 is eligible for fetching LLIs lli-bus-interface-ahb2: type: boolean description: if AHB master 2 is eligible for fetching LLIs mem-bus-interface-ahb1: type: boolean description: if AHB master 1 is eligible for fetching memory contents mem-bus-interface-ahb2: type: boolean description: if AHB master 2 is eligible for fetching memory contents memcpy-burst-size: $ref: /schemas/types.yaml#/definitions/uint32 enum: - 1 - 4 - 8 - 16 - 32 - 64 - 128 - 256 description: the size of the bursts for memcpy memcpy-bus-width: $ref: /schemas/types.yaml#/definitions/uint32 enum: - 8 - 16 - 32 - 64 description: bus width used for memcpy in bits. FTDMAC020 also accept 64 bits resets: maxItems: 1 required: - reg - interrupts - clocks - clock-names - "#dma-cells" unevaluatedProperties: false examples: - | dmac0: dma-controller@10130000 { compatible = "arm,pl080", "arm,primecell"; reg = <0x10130000 0x1000>; interrupt-parent = <&vica>; interrupts = <15>; clocks = <&hclkdma0>; clock-names = "apb_pclk"; lli-bus-interface-ahb1; lli-bus-interface-ahb2; mem-bus-interface-ahb2; memcpy-burst-size = <256>; memcpy-bus-width = <32>; #dma-cells = <2>; }; - | #include <dt-bindings/interrupt-controller/irq.h> #include <dt-bindings/reset/cortina,gemini-reset.h> #include <dt-bindings/clock/cortina,gemini-clock.h> dma-controller@67000000 { compatible = "faraday,ftdma020", "arm,pl080", "arm,primecell"; /* Faraday Technology FTDMAC020 variant */ arm,primecell-periphid = <0x0003b080>; reg = <0x67000000 0x1000>; interrupts = <9 IRQ_TYPE_EDGE_RISING>; resets = <&syscon GEMINI_RESET_DMAC>; clocks = <&syscon GEMINI_CLK_AHB>; clock-names = "apb_pclk"; /* Bus interface AHB1 (AHB0) is totally tilted */ lli-bus-interface-ahb2; mem-bus-interface-ahb2; memcpy-burst-size = <256>; memcpy-bus-width = <32>; #dma-cells = <2>; }; |