Based on kernel version 6.11
. Page generated on 2024-09-24 08:21 EST
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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 | # SPDX-License-Identifier: GPL-2.0-only %YAML 1.2 --- $id: http://devicetree.org/schemas/i2c/snps,designware-i2c.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: Synopsys DesignWare APB I2C Controller maintainers: - Jarkko Nikula <jarkko.nikula@linux.intel.com> allOf: - $ref: /schemas/i2c/i2c-controller.yaml# - if: properties: compatible: not: contains: const: mscc,ocelot-i2c then: properties: reg: maxItems: 1 properties: compatible: oneOf: - description: Generic Synopsys DesignWare I2C controller const: snps,designware-i2c - description: Microsemi Ocelot SoCs I2C controller items: - const: mscc,ocelot-i2c - const: snps,designware-i2c - description: Baikal-T1 SoC System I2C controller const: baikal,bt1-sys-i2c - description: T-HEAD TH1520 SoCs I2C controller items: - const: thead,th1520-i2c - const: snps,designware-i2c reg: minItems: 1 items: - description: DW APB I2C controller memory mapped registers - description: | ICPU_CFG:TWI_DELAY registers to setup the SDA hold time. This registers are specific to the Ocelot I2C-controller. interrupts: maxItems: 1 clocks: minItems: 1 items: - description: I2C controller reference clock source - description: APB interface clock source clock-names: minItems: 1 items: - const: ref - const: pclk resets: maxItems: 1 clock-frequency: description: Desired I2C bus clock frequency in Hz enum: [100000, 400000, 1000000, 3400000] default: 400000 i2c-sda-hold-time-ns: description: | The property should contain the SDA hold time in nanoseconds. This option is only supported in hardware blocks version 1.11a or newer or on Microsemi SoCs. i2c-scl-falling-time-ns: description: | The property should contain the SCL falling time in nanoseconds. This value is used to compute the tLOW period. default: 300 i2c-sda-falling-time-ns: description: | The property should contain the SDA falling time in nanoseconds. This value is used to compute the tHIGH period. default: 300 dmas: items: - description: TX DMA Channel - description: RX DMA Channel dma-names: items: - const: tx - const: rx unevaluatedProperties: false required: - compatible - reg - interrupts examples: - | i2c@f0000 { compatible = "snps,designware-i2c"; reg = <0xf0000 0x1000>; interrupts = <11>; clock-frequency = <400000>; }; - | i2c@1120000 { compatible = "snps,designware-i2c"; reg = <0x1120000 0x1000>; interrupts = <12 1>; clock-frequency = <400000>; i2c-sda-hold-time-ns = <300>; i2c-sda-falling-time-ns = <300>; i2c-scl-falling-time-ns = <300>; }; - | i2c@2000 { compatible = "snps,designware-i2c"; reg = <0x2000 0x100>; #address-cells = <1>; #size-cells = <0>; clock-frequency = <400000>; clocks = <&i2cclk>; interrupts = <0>; eeprom@64 { compatible = "atmel,24c02"; reg = <0x64>; }; }; - | i2c@100400 { compatible = "mscc,ocelot-i2c", "snps,designware-i2c"; reg = <0x100400 0x100>, <0x198 0x8>; pinctrl-0 = <&i2c_pins>; pinctrl-names = "default"; interrupts = <8>; clocks = <&ahb_clk>; }; ... |