Based on kernel version 6.11
. Page generated on 2024-09-24 08:21 EST
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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 | # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2 --- $id: http://devicetree.org/schemas/i2c/aspeed,i2c.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: ASPEED I2C on the AST24XX, AST25XX, and AST26XX SoCs maintainers: - Rayn Chen <rayn_chen@aspeedtech.com> allOf: - $ref: /schemas/i2c/i2c-controller.yaml# properties: compatible: enum: - aspeed,ast2400-i2c-bus - aspeed,ast2500-i2c-bus - aspeed,ast2600-i2c-bus reg: minItems: 1 items: - description: address offset and range of bus - description: address offset and range of bus buffer interrupts: maxItems: 1 clocks: maxItems: 1 description: root clock of bus, should reference the APB clock in the second cell resets: maxItems: 1 bus-frequency: minimum: 500 maximum: 4000000 default: 100000 description: frequency of the bus clock in Hz defaults to 100 kHz when not specified multi-master: type: boolean description: states that there is another master active on this bus required: - reg - compatible - clocks - resets unevaluatedProperties: false examples: - | #include <dt-bindings/clock/aspeed-clock.h> i2c@40 { #address-cells = <1>; #size-cells = <0>; compatible = "aspeed,ast2500-i2c-bus"; reg = <0x40 0x40>; clocks = <&syscon ASPEED_CLK_APB>; resets = <&syscon ASPEED_RESET_I2C>; bus-frequency = <100000>; interrupts = <0>; interrupt-parent = <&i2c_ic>; }; |