# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
%YAML 1.2
---

$id: http://devicetree.org/schemas/display/msm/qcom,adreno-rgmu.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: RGMU attached to certain Adreno GPUs

maintainers:
  - Rob Clark <robin.clark@oss.qualcomm.com>

description:
  RGMU (Reduced Graphics Management Unit) IP is present in some GPUs that
  belong to Adreno A6xx family. It is a small state machine that helps to
  toggle the GX GDSC (connected to CX rail) to implement IFPC feature and save
  power.

properties:
  compatible:
    items:
      - const: qcom,adreno-rgmu-612.0
      - const: qcom,adreno-rgmu

  reg:
    items:
      - description: Core RGMU registers

  clocks:
    items:
      - description: GMU clock
      - description: GPU CX clock
      - description: GPU AXI clock
      - description: GPU MEMNOC clock
      - description: GPU SMMU vote clock

  clock-names:
    items:
      - const: gmu
      - const: cxo
      - const: axi
      - const: memnoc
      - const: smmu_vote

  power-domains:
    items:
      - description: CX GDSC power domain
      - description: GX GDSC power domain

  power-domain-names:
    items:
      - const: cx
      - const: gx

  interrupts:
    items:
      - description: GMU OOB interrupt
      - description: GMU interrupt

  interrupt-names:
    items:
      - const: oob
      - const: gmu

  operating-points-v2: true
  opp-table:
    type: object

required:
  - compatible
  - reg
  - clocks
  - clock-names
  - power-domains
  - power-domain-names
  - interrupts
  - interrupt-names
  - operating-points-v2

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/qcom,qcs615-gpucc.h>
    #include <dt-bindings/clock/qcom,qcs615-gcc.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/power/qcom,rpmhpd.h>
 
    gmu@506a000 {
        compatible = "qcom,adreno-rgmu-612.0", "qcom,adreno-rgmu";
 
        reg = <0x05000000 0x90000>;
 
        clocks = <&gpucc GPU_CC_CX_GMU_CLK>,
                 <&gpucc GPU_CC_CXO_CLK>,
                 <&gcc GCC_DDRSS_GPU_AXI_CLK>,
                 <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
                 <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>;
        clock-names = "gmu",
                      "cxo",
                      "axi",
                      "memnoc",
                      "smmu_vote";
 
        power-domains = <&gpucc CX_GDSC>,
                        <&gpucc GX_GDSC>;
        power-domain-names = "cx",
                             "gx";
 
        interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
        interrupt-names = "oob",
                          "gmu";
 
        operating-points-v2 = <&gmu_opp_table>;
 
        gmu_opp_table: opp-table {
            compatible = "operating-points-v2";
 
            opp-200000000 {
                opp-hz = /bits/ 64 <200000000>;
                required-opps = <&rpmhpd_opp_low_svs>;
            };
        };
    };