# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/msm/qcom,sc7280-mdss.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm SC7280 Display MDSS

maintainers:
  - Krishna Manikandan <quic_mkrishn@quicinc.com>

description:
  Device tree bindings for MSM Mobile Display Subsystem (MDSS) that encapsulates
  sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree
  bindings of MDSS are mentioned for SC7280.

$ref: /schemas/display/msm/mdss-common.yaml#

properties:
  compatible:
    const: qcom,sc7280-mdss

  clocks:
    items:
      - description: Display AHB clock from gcc
      - description: Display AHB clock from dispcc
      - description: Display core clock

  clock-names:
    items:
      - const: iface
      - const: ahb
      - const: core

  iommus:
    maxItems: 1

  interconnects:
    items:
      - description: Interconnect path from mdp0 port to the data bus
      - description: Interconnect path from CPU to the reg bus

  interconnect-names:
    items:
      - const: mdp0-mem
      - const: cpu-cfg

patternProperties:
  "^display-controller@[0-9a-f]+$":
    type: object
    additionalProperties: true

    properties:
      compatible:
        const: qcom,sc7280-dpu
 
  "^displayport-controller@[0-9a-f]+$":
    type: object
    additionalProperties: true

    properties:
      compatible:
        const: qcom,sc7280-dp
 
  "^dsi@[0-9a-f]+$":
    type: object
    additionalProperties: true

    properties:
      compatible:
        items:
          - const: qcom,sc7280-dsi-ctrl
          - const: qcom,mdss-dsi-ctrl
 
  "^edp@[0-9a-f]+$":
    type: object
    additionalProperties: true

    properties:
      compatible:
        const: qcom,sc7280-edp
 
  "^phy@[0-9a-f]+$":
    type: object
    additionalProperties: true

    properties:
      compatible:
        enum:
          - qcom,sc7280-dsi-phy-7nm
          - qcom,sc7280-edp-phy

required:
  - compatible

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/clock/qcom,dispcc-sc7280.h>
    #include <dt-bindings/clock/qcom,gcc-sc7280.h>
    #include <dt-bindings/clock/qcom,rpmh.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/interconnect/qcom,sc7280.h>
    #include <dt-bindings/power/qcom-rpmpd.h>
 
    display-subsystem@ae00000 {
        #address-cells = <1>;
        #size-cells = <1>;
        compatible = "qcom,sc7280-mdss";
        reg = <0xae00000 0x1000>;
        reg-names = "mdss";
        power-domains = <&dispcc DISP_CC_MDSS_CORE_GDSC>;
        clocks = <&gcc GCC_DISP_AHB_CLK>,
                 <&dispcc DISP_CC_MDSS_AHB_CLK>,
                 <&dispcc DISP_CC_MDSS_MDP_CLK>;
        clock-names = "iface",
                      "ahb",
                      "core";
 
        interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
        interrupt-controller;
        #interrupt-cells = <1>;
 
        interconnects = <&mmss_noc MASTER_MDP0 &mc_virt SLAVE_EBI1>,
                        <&gem_noc MASTER_APPSS_PROC &cnoc2 SLAVE_DISPLAY_CFG>;
        interconnect-names = "mdp0-mem",
                             "cpu-cfg";
 
        iommus = <&apps_smmu 0x900 0x402>;
        ranges;
 
        display-controller@ae01000 {
            compatible = "qcom,sc7280-dpu";
            reg = <0x0ae01000 0x8f000>,
                  <0x0aeb0000 0x2008>;
 
            reg-names = "mdp", "vbif";
 
            clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
                     <&gcc GCC_DISP_SF_AXI_CLK>,
                     <&dispcc DISP_CC_MDSS_AHB_CLK>,
                     <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
                     <&dispcc DISP_CC_MDSS_MDP_CLK>,
                     <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
            clock-names = "bus",
                          "nrt_bus",
                          "iface",
                          "lut",
                          "core",
                          "vsync";
 
            interrupt-parent = <&mdss>;
            interrupts = <0>;
            power-domains = <&rpmhpd SC7280_CX>;
            operating-points-v2 = <&mdp_opp_table>;
 
            ports {
                #address-cells = <1>;
                #size-cells = <0>;
 
                port@0 {
                    reg = <0>;
                    dpu_intf1_out: endpoint {
                        remote-endpoint = <&dsi0_in>;
                    };
                };
 
                port@1 {
                    reg = <1>;
                    dpu_intf5_out: endpoint {
                        remote-endpoint = <&edp_in>;
                    };
                };
 
                port@2 {
                    reg = <2>;
                    dpu_intf0_out: endpoint {
                        remote-endpoint = <&dp_in>;
                    };
                };
            };
        };
 
        dsi@ae94000 {
            compatible = "qcom,sc7280-dsi-ctrl", "qcom,mdss-dsi-ctrl";
            reg = <0x0ae94000 0x400>;
            reg-names = "dsi_ctrl";
 
            interrupt-parent = <&mdss>;
            interrupts = <4>;
 
            clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
                     <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
                     <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
                     <&dispcc DISP_CC_MDSS_ESC0_CLK>,
                     <&dispcc DISP_CC_MDSS_AHB_CLK>,
                     <&gcc GCC_DISP_HF_AXI_CLK>;
            clock-names = "byte",
                          "byte_intf",
                          "pixel",
                          "core",
                          "iface",
                          "bus";
 
            assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
                              <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
            assigned-clock-parents = <&mdss_dsi_phy 0>, <&mdss_dsi_phy 1>;
 
            operating-points-v2 = <&dsi_opp_table>;
            power-domains = <&rpmhpd SC7280_CX>;
 
            phys = <&mdss_dsi_phy>;
            phy-names = "dsi";
 
            #address-cells = <1>;
            #size-cells = <0>;
 
            ports {
                #address-cells = <1>;
                #size-cells = <0>;
 
                port@0 {
                    reg = <0>;
                    dsi0_in: endpoint {
                        remote-endpoint = <&dpu_intf1_out>;
                    };
                };
 
                port@1 {
                    reg = <1>;
                    dsi0_out: endpoint {
                    };
                };
            };
 
            dsi_opp_table: opp-table {
                compatible = "operating-points-v2";
 
                opp-187500000 {
                    opp-hz = /bits/ 64 <187500000>;
                    required-opps = <&rpmhpd_opp_low_svs>;
                };
 
                opp-300000000 {
                    opp-hz = /bits/ 64 <300000000>;
                    required-opps = <&rpmhpd_opp_svs>;
                };
 
                opp-358000000 {
                    opp-hz = /bits/ 64 <358000000>;
                    required-opps = <&rpmhpd_opp_svs_l1>;
                };
            };
        };
 
        mdss_dsi_phy: phy@ae94400 {
            compatible = "qcom,sc7280-dsi-phy-7nm";
            reg = <0x0ae94400 0x200>,
                  <0x0ae94600 0x280>,
                  <0x0ae94900 0x280>;
            reg-names = "dsi_phy",
                        "dsi_phy_lane",
                        "dsi_pll";
 
            #clock-cells = <1>;
            #phy-cells = <0>;
 
            clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
                     <&rpmhcc RPMH_CXO_CLK>;
            clock-names = "iface", "ref";
 
            vdds-supply = <&vreg_dsi_supply>;
        };
 
        edp@aea0000 {
            compatible = "qcom,sc7280-edp";
            pinctrl-names = "default";
            pinctrl-0 = <&edp_hot_plug_det>;
 
            reg = <0xaea0000 0x200>,
                  <0xaea0200 0x200>,
                  <0xaea0400 0xc00>,
                  <0xaea1000 0x400>;
 
            interrupt-parent = <&mdss>;
            interrupts = <14>;
 
            clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
                     <&dispcc DISP_CC_MDSS_EDP_AUX_CLK>,
                     <&dispcc DISP_CC_MDSS_EDP_LINK_CLK>,
                     <&dispcc DISP_CC_MDSS_EDP_LINK_INTF_CLK>,
                     <&dispcc DISP_CC_MDSS_EDP_PIXEL_CLK>;
            clock-names = "core_iface",
                          "core_aux",
                          "ctrl_link",
                          "ctrl_link_iface",
                          "stream_pixel";
            assigned-clocks = <&dispcc DISP_CC_MDSS_EDP_LINK_CLK_SRC>,
                              <&dispcc DISP_CC_MDSS_EDP_PIXEL_CLK_SRC>;
            assigned-clock-parents = <&mdss_edp_phy 0>, <&mdss_edp_phy 1>;
 
            phys = <&mdss_edp_phy>;
            phy-names = "dp";
 
            operating-points-v2 = <&edp_opp_table>;
            power-domains = <&rpmhpd SC7280_CX>;
 
            ports {
                #address-cells = <1>;
                #size-cells = <0>;
 
                port@0 {
                    reg = <0>;
                    edp_in: endpoint {
                        remote-endpoint = <&dpu_intf5_out>;
                    };
                };
 
                port@1 {
                    reg = <1>;
                    mdss_edp_out: endpoint { };
                };
            };
 
            edp_opp_table: opp-table {
                compatible = "operating-points-v2";
 
                opp-160000000 {
                    opp-hz = /bits/ 64 <160000000>;
                    required-opps = <&rpmhpd_opp_low_svs>;
                };
 
                opp-270000000 {
                    opp-hz = /bits/ 64 <270000000>;
                    required-opps = <&rpmhpd_opp_svs>;
                };
 
                opp-540000000 {
                    opp-hz = /bits/ 64 <540000000>;
                    required-opps = <&rpmhpd_opp_nom>;
                };
 
                opp-810000000 {
                    opp-hz = /bits/ 64 <810000000>;
                    required-opps = <&rpmhpd_opp_nom>;
                };
            };
        };
 
        mdss_edp_phy: phy@aec2a00 {
            compatible = "qcom,sc7280-edp-phy";
 
            reg = <0xaec2a00 0x19c>,
                  <0xaec2200 0xa0>,
                  <0xaec2600 0xa0>,
                  <0xaec2000 0x1c0>;
 
            clocks = <&rpmhcc RPMH_CXO_CLK>,
                     <&gcc GCC_EDP_CLKREF_EN>;
            clock-names = "aux",
                          "cfg_ahb";
 
            #clock-cells = <1>;
            #phy-cells = <0>;
        };
 
        displayport-controller@ae90000 {
            compatible = "qcom,sc7280-dp";
 
            reg = <0xae90000 0x200>,
                  <0xae90200 0x200>,
                  <0xae90400 0xc00>,
                  <0xae91000 0x400>,
                  <0xae91400 0x400>;
 
            interrupt-parent = <&mdss>;
            interrupts = <12>;
 
            clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
                     <&dispcc DISP_CC_MDSS_DP_AUX_CLK>,
                     <&dispcc DISP_CC_MDSS_DP_LINK_CLK>,
                     <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>,
                     <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>;
            clock-names = "core_iface",
                          "core_aux",
                          "ctrl_link",
                          "ctrl_link_iface",
                          "stream_pixel";
            assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>,
                              <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>;
            assigned-clock-parents = <&dp_phy 0>, <&dp_phy 1>;
            phys = <&dp_phy>;
            phy-names = "dp";
 
            operating-points-v2 = <&dp_opp_table>;
            power-domains = <&rpmhpd SC7280_CX>;
 
            #sound-dai-cells = <0>;
 
            ports {
                #address-cells = <1>;
                #size-cells = <0>;
 
                port@0 {
                    reg = <0>;
                    dp_in: endpoint {
                        remote-endpoint = <&dpu_intf0_out>;
                    };
                };
 
                port@1 {
                    reg = <1>;
                    dp_out: endpoint { };
                };
            };
 
            dp_opp_table: opp-table {
                compatible = "operating-points-v2";
 
                opp-160000000 {
                    opp-hz = /bits/ 64 <160000000>;
                    required-opps = <&rpmhpd_opp_low_svs>;
                };
 
                opp-270000000 {
                    opp-hz = /bits/ 64 <270000000>;
                    required-opps = <&rpmhpd_opp_svs>;
                };
 
                opp-540000000 {
                    opp-hz = /bits/ 64 <540000000>;
                    required-opps = <&rpmhpd_opp_svs_l1>;
                };
 
                opp-810000000 {
                    opp-hz = /bits/ 64 <810000000>;
                    required-opps = <&rpmhpd_opp_nom>;
                };
            };
        };
    };
...