Based on kernel version 6.11
. Page generated on 2024-09-24 08:21 EST
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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 | # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause %YAML 1.2 --- $id: http://devicetree.org/schemas/display/msm/mdss-common.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: Qualcomm Display MDSS common properties maintainers: - Krishna Manikandan <quic_mkrishn@quicinc.com> - Dmitry Baryshkov <dmitry.baryshkov@linaro.org> - Rob Clark <robdclark@gmail.com> description: Device tree bindings for MSM Mobile Display Subsystem(MDSS) that encapsulates sub-blocks like DPU display controller, DSI and DP interfaces etc. # Do not select this by default, otherwise it is also selected for qcom,mdss # devices. select: false properties: $nodename: pattern: "^display-subsystem@[0-9a-f]+$" reg: maxItems: 1 reg-names: const: mdss power-domains: maxItems: 1 clocks: minItems: 2 maxItems: 4 clock-names: minItems: 2 maxItems: 4 interrupts: maxItems: 1 interrupt-controller: true "#address-cells": true "#size-cells": true "#interrupt-cells": const: 1 iommus: minItems: 1 items: - description: Phandle to apps_smmu node with SID mask for Hard-Fail port0 - description: Phandle to apps_smmu node with SID mask for Hard-Fail port1 ranges: true # This is not a perfect description, but it's impossible to discern and match # the entries like we do with interconnect-names interconnects: minItems: 1 items: - description: Interconnect path from mdp0 (or a single mdp) port to the data bus - description: Interconnect path from mdp1 port to the data bus - description: Interconnect path from CPU to the reg bus interconnect-names: oneOf: - minItems: 1 items: - const: mdp0-mem - const: cpu-cfg - minItems: 2 items: - const: mdp0-mem - const: mdp1-mem - const: cpu-cfg resets: items: - description: MDSS_CORE reset memory-region: maxItems: 1 description: Phandle to a node describing a reserved framebuffer memory region. For example, the splash memory region set up by the bootloader. required: - reg - reg-names - power-domains - clocks - interrupts - interrupt-controller - iommus - ranges additionalProperties: true |