Based on kernel version 6.17. Page generated on 2025-10-03 10:04 EST.
| 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 | # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2 --- $id: http://devicetree.org/schemas/display/imx/fsl,imx8qxp-dc.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: Freescale i.MX8qxp Display Controller description: | The Freescale i.MX8qxp Display Controller(DC) is comprised of three main components that include a blit engine for 2D graphics accelerations, display controller for display output processing, as well as a command sequencer. Display buffers Source buffers (AXI read master) (AXI read master) | .......... | | | | +---------------------------+------------+------------------+-+-+------+ | Display Controller (DC) | .......... | | | | | | | | | | | | | @@@@@@@@@@@ +----------+------------+------------+ | | | | A | | Command | | V V | | | | | X <-+->| Sequencer | | @@@@@@@@@@@@@@@@@@@@@@@@@@@@ | V V V | I | | (AXI CLK) | | | | | @@@@@@@@@@ | | @@@@@@@@@@@ | | Pixel Engine | | | | | | | | | (AXI CLK) | | | | | | V | @@@@@@@@@@@@@@@@@@@@@@@@@@@@ | | | | A | *********** | | | | | | | Blit | | H <-+->| Configure | | V V V V | | Engine | | B | | (CFG CLK) | | 00000000000 11111111111 | | (AXI CLK)| | | *********** | | Display | | Display | | | | | | | | Engine | | Engine | | | | | | | | (Disp CLK)| | (Disp CLK)| | | | | | @@@@@@@@@@@ | 00000000000 11111111111 | @@@@@@@@@@ | I | | Common | | | | | | | R <-+--| Control | | | Display | | | | Q | | (AXI CLK) | | | Controller | | | | | @@@@@@@@@@@ +------------------------------------+ | | | | | ^ | | +--------------------------+----------------+-------+---------+--------+ ^ | | | | | V V | V Clocks & Resets Display Display Panic Destination Output0 Output1 Control buffer (AXI write master) maintainers: - Liu Ying <victor.liu@nxp.com> properties: compatible: const: fsl,imx8qxp-dc reg: maxItems: 1 clocks: maxItems: 1 resets: maxItems: 2 reset-names: items: - const: axi - const: cfg power-domains: maxItems: 1 "#address-cells": const: 1 "#size-cells": const: 1 ranges: true patternProperties: "^command-sequencer@[0-9a-f]+$": type: object additionalProperties: true properties: compatible: const: fsl,imx8qxp-dc-command-sequencer "^display-engine@[0-9a-f]+$": type: object additionalProperties: true properties: compatible: const: fsl,imx8qxp-dc-display-engine "^interrupt-controller@[0-9a-f]+$": type: object additionalProperties: true properties: compatible: const: fsl,imx8qxp-dc-intc "^pixel-engine@[0-9a-f]+$": type: object additionalProperties: true properties: compatible: const: fsl,imx8qxp-dc-pixel-engine "^pmu@[0-9a-f]+$": type: object additionalProperties: true properties: compatible: const: fsl,imx8qxp-dc-axi-performance-counter required: - compatible - reg - clocks - power-domains - "#address-cells" - "#size-cells" - ranges additionalProperties: false examples: - | #include <dt-bindings/clock/imx8-lpcg.h> #include <dt-bindings/firmware/imx/rsrc.h> display-controller@56180000 { compatible = "fsl,imx8qxp-dc"; reg = <0x56180000 0x40000>; clocks = <&dc0_lpcg IMX_LPCG_CLK_4>; power-domains = <&pd IMX_SC_R_DC_0>; #address-cells = <1>; #size-cells = <1>; ranges; interrupt-controller@56180040 { compatible = "fsl,imx8qxp-dc-intc"; reg = <0x56180040 0x60>; clocks = <&dc0_lpcg IMX_LPCG_CLK_5>; interrupt-controller; interrupt-parent = <&dc0_irqsteer>; #interrupt-cells = <1>; interrupts = <448>, <449>, <450>, <64>, <65>, <66>, <67>, <68>, <69>, <70>, <193>, <194>, <195>, <196>, <197>, <72>, <73>, <74>, <75>, <76>, <77>, <78>, <79>, <80>, <81>, <199>, <200>, <201>, <202>, <203>, <204>, <205>, <206>, <207>, <208>, <5>, <0>, <1>, <2>, <3>, <4>, <82>, <83>, <84>, <85>, <209>, <210>, <211>, <212>; interrupt-names = "store9_shdload", "store9_framecomplete", "store9_seqcomplete", "extdst0_shdload", "extdst0_framecomplete", "extdst0_seqcomplete", "extdst4_shdload", "extdst4_framecomplete", "extdst4_seqcomplete", "extdst1_shdload", "extdst1_framecomplete", "extdst1_seqcomplete", "extdst5_shdload", "extdst5_framecomplete", "extdst5_seqcomplete", "disengcfg_shdload0", "disengcfg_framecomplete0", "disengcfg_seqcomplete0", "framegen0_int0", "framegen0_int1", "framegen0_int2", "framegen0_int3", "sig0_shdload", "sig0_valid", "sig0_error", "disengcfg_shdload1", "disengcfg_framecomplete1", "disengcfg_seqcomplete1", "framegen1_int0", "framegen1_int1", "framegen1_int2", "framegen1_int3", "sig1_shdload", "sig1_valid", "sig1_error", "reserved", "cmdseq_error", "comctrl_sw0", "comctrl_sw1", "comctrl_sw2", "comctrl_sw3", "framegen0_primsync_on", "framegen0_primsync_off", "framegen0_secsync_on", "framegen0_secsync_off", "framegen1_primsync_on", "framegen1_primsync_off", "framegen1_secsync_on", "framegen1_secsync_off"; }; pixel-engine@56180800 { compatible = "fsl,imx8qxp-dc-pixel-engine"; reg = <0x56180800 0xac00>; clocks = <&dc0_lpcg IMX_LPCG_CLK_5>; #address-cells = <1>; #size-cells = <1>; ranges; }; display-engine@5618b400 { compatible = "fsl,imx8qxp-dc-display-engine"; reg = <0x5618b400 0x14>, <0x5618b800 0x1c00>; reg-names = "top", "cfg"; interrupt-parent = <&dc0_intc>; interrupts = <15>, <16>, <17>; interrupt-names = "shdload", "framecomplete", "seqcomplete"; power-domains = <&pd IMX_SC_R_DC_0_PLL_0>; #address-cells = <1>; #size-cells = <1>; ranges; }; }; |