Documentation / devicetree / bindings / display / imx / fsl,imx8qxp-dc-axi-performance-counter.yaml


Based on kernel version 6.17. Page generated on 2025-10-03 10:04 EST.

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/imx/fsl,imx8qxp-dc-axi-performance-counter.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Freescale i.MX8qxp Display Controller AXI Performance Counter

description: |
  Performance counters are provided to allow measurement of average bandwidth
  and latency during operation. The following features are supported:
 
  * Manual and timer controlled measurement mode.
 
  * Measurement counters:
    - GLOBAL_COUNTER for overall measurement time
    - BUSY_COUNTER for number of data bus busy cycles
    - DATA_COUNTER for number of data transfer cycles
    - TRANSFER_COUNTER for number of transfers
    - ADDRBUSY_COUNTER for number of address bus busy cycles
    - LATENCY_COUNTER for average latency
 
  * Counter overflow detection.
 
  * Outstanding Transfer Counters (OTC) which are used for latency measurement
    have to run immediately after reset, but can be disabled by software when
    there is no need for latency measurement.

maintainers:
  - Liu Ying <victor.liu@nxp.com>

properties:
  compatible:
    const: fsl,imx8qxp-dc-axi-performance-counter

  reg:
    maxItems: 1

  clocks:
    maxItems: 1

required:
  - compatible
  - reg
  - clocks

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/imx8-lpcg.h>
 
    pmu@5618f000 {
        compatible = "fsl,imx8qxp-dc-axi-performance-counter";
        reg = <0x5618f000 0x90>;
        clocks = <&dc0_lpcg IMX_LPCG_CLK_5>;
    };