Based on kernel version 6.17
. Page generated on 2025-10-03 10:04 EST
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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 | # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2 --- $id: http://devicetree.org/schemas/display/imx/fsl,imx8qxp-dc-store.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: Freescale i.MX8qxp Display Controller Store Unit description: | The Store unit is the interface between the internal pixel processing pipeline, which is 30-bit RGB plus 8-bit Alpha, and the AXI bus for destination buffer access. It is used for the destination of Blit Engines. It comprises a set of built-in functions to generate a wide range of buffer formats. Note, that these are exactly inverse to corresponding functions in the Fetch Unit. +------X-------------------------+ | | Store Unit | | V | | +-------+ | | | Gamma | Gamma apply | | +-------+ | | | | | V | | +-------+ | | | Color | RGB to YUV | | +-------+ | | | | | V | | +-------+ | | | Chroma| YUV444 to 422 | | +-------+ | | | | | V | | +-------+ | | | Reduce| Bit width reduction | | | | dithering | | +-------+ | | | | | V | | +-------+ | | | Pack | RGBA/YUV to RAW | | | Encode| or Compression | | +-------+ | | | | | V | +------X-------------------------+ maintainers: - Liu Ying <victor.liu@nxp.com> properties: compatible: const: fsl,imx8qxp-dc-store reg: maxItems: 2 reg-names: items: - const: pec - const: cfg interrupts: maxItems: 3 interrupt-names: items: - const: shdload - const: framecomplete - const: seqcomplete fsl,lts: $ref: /schemas/types.yaml#/definitions/phandle description: Optional Linear Tile Store associated with the Store Unit. required: - compatible - reg - reg-names - interrupts - interrupt-names additionalProperties: false examples: - | store@56180940 { compatible = "fsl,imx8qxp-dc-store"; reg = <0x56180940 0x1c>, <0x56184000 0x5c>; reg-names = "pec", "cfg"; interrupt-parent = <&dc0_intc>; interrupts = <0>, <1>, <2>; interrupt-names = "shdload", "framecomplete", "seqcomplete"; }; |