# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/imx/fsl,imx8qxp-dc-display-engine.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Freescale i.MX8qxp Display Controller Display Engine

description:
  All Processing Units that operate in a display clock domain. Pixel pipeline
  is driven by a video timing and cannot be stalled. Implements all display
  specific processing.

maintainers:
  - Liu Ying <victor.liu@nxp.com>

properties:
  compatible:
    const: fsl,imx8qxp-dc-display-engine

  reg:
    maxItems: 2

  reg-names:
    items:
      - const: top
      - const: cfg

  resets:
    maxItems: 1

  interrupts:
    maxItems: 3

  interrupt-names:
    items:
      - const: shdload
      - const: framecomplete
      - const: seqcomplete

  power-domains:
    maxItems: 1
 
  "#address-cells":
    const: 1
 
  "#size-cells":
    const: 1

  ranges: true

patternProperties:
  "^dither@[0-9a-f]+$":
    type: object
    additionalProperties: true

    properties:
      compatible:
        const: fsl,imx8qxp-dc-dither
 
  "^framegen@[0-9a-f]+$":
    type: object
    additionalProperties: true

    properties:
      compatible:
        const: fsl,imx8qxp-dc-framegen
 
  "^gammacor@[0-9a-f]+$":
    type: object
    additionalProperties: true

    properties:
      compatible:
        const: fsl,imx8qxp-dc-gammacor
 
  "^matrix@[0-9a-f]+$":
    type: object
    additionalProperties: true

    properties:
      compatible:
        const: fsl,imx8qxp-dc-matrix
 
  "^signature@[0-9a-f]+$":
    type: object
    additionalProperties: true

    properties:
      compatible:
        const: fsl,imx8qxp-dc-signature
 
  "^tcon@[0-9a-f]+$":
    type: object
    additionalProperties: true

    properties:
      compatible:
        const: fsl,imx8qxp-dc-tcon

required:
  - compatible
  - reg
  - reg-names
  - interrupts
  - interrupt-names
  - power-domains
  - "#address-cells"
  - "#size-cells"
  - ranges

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/imx8-lpcg.h>
    #include <dt-bindings/firmware/imx/rsrc.h>
 
    display-engine@5618b400 {
        compatible = "fsl,imx8qxp-dc-display-engine";
        reg = <0x5618b400 0x14>, <0x5618b800 0x1c00>;
        reg-names = "top", "cfg";
        interrupt-parent = <&dc0_intc>;
        interrupts = <15>, <16>, <17>;
        interrupt-names = "shdload", "framecomplete", "seqcomplete";
        power-domains = <&pd IMX_SC_R_DC_0_PLL_0>;
        #address-cells = <1>;
        #size-cells = <1>;
        ranges;
 
        framegen@5618b800 {
            compatible = "fsl,imx8qxp-dc-framegen";
            reg = <0x5618b800 0x98>;
            clocks = <&dc0_disp_lpcg IMX_LPCG_CLK_0>;
            interrupt-parent = <&dc0_intc>;
            interrupts = <18>, <19>, <20>, <21>, <41>, <42>, <43>, <44>;
            interrupt-names = "int0", "int1", "int2", "int3",
                              "primsync_on", "primsync_off",
                              "secsync_on", "secsync_off";
        };
 
        tcon@5618c800 {
            compatible = "fsl,imx8qxp-dc-tcon";
            reg = <0x5618c800 0x588>;
 
            port {
                dc0_disp0_dc0_pixel_combiner_ch0: endpoint {
                    remote-endpoint = <&dc0_pixel_combiner_ch0_dc0_disp0>;
                };
            };
        };
    };