# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/bridge/renesas,r9a08g046-lvds.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Renesas RZ/G3L LVDS Encoder

maintainers:
  - Biju Das <biju.das.jz@bp.renesas.com>
  - Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>

description: |
  This binding describes the LVDS encoder embedded in the Renesas RZ/G3L
  SoC. The encoder can operate in LVDS Single-link mode with 4 lanes
  (Data) + 1 lane (Clock).

properties:
  compatible:
    const: renesas,r9a08g046-lvds

  reg:
    maxItems: 1

  clocks:
    items:
      - description: Peripheral clock
      - description: PHY clock
      - description: Dot clock

  clock-names:
    items:
      - const: pclk
      - const: phyclk
      - const: dotclk

  resets:
    items:
      - description: LVDS_RESET_N
      - description: MIPI_DSI_PRESET_N
      - description: MIPI_DSI_CMN_RSTB
      - description: MIPI_DSI_ARESET_N

  reset-names:
    items:
      - const: lvdrst
      - const: prst
      - const: rst
      - const: arst

  power-domains:
    maxItems: 1

  ports:
    $ref: /schemas/graph.yaml#/properties/ports

    properties:
      port@0:
        $ref: /schemas/graph.yaml#/properties/port
        description: Input channel, directly connected to the Display Unit.

      port@1:
        $ref: /schemas/graph.yaml#/properties/port
        description: |
          Output channel, directly connected to the LVDS panel or bridge.

    required:
      - port@0
      - port@1

required:
  - compatible
  - reg
  - clocks
  - clock-names
  - resets
  - reset-names
  - power-domains
  - ports

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/renesas,r9a08g046-cpg.h>
 
    lvds@108a0000 {
        compatible = "renesas,r9a08g046-lvds";
        reg = <0x108a0000 0x10000>;
        clocks = <&cpg CPG_MOD R9A08G046_MIPI_DSI_PCLK>,
                 <&cpg CPG_MOD R9A08G046_LVDS_PLLCLK>,
                 <&cpg CPG_MOD R9A08G046_LVDS_CLK_DOT0>;
        clock-names = "pclk", "phyclk", "dotclk";
        resets = <&cpg R9A08G046_LVDS_RESET_N>,
                 <&cpg R9A08G046_MIPI_DSI_PRESET_N>,
                 <&cpg R9A08G046_MIPI_DSI_CMN_RSTB>,
                 <&cpg R9A08G046_MIPI_DSI_ARESET_N>;
        reset-names = "lvdrst", "prst", "rst", "arst";
        power-domains = <&cpg>;
 
        ports {
            #address-cells = <1>;
            #size-cells = <0>;
 
            port@0 {
                reg = <0>;
                lvds0_in: endpoint {
                    remote-endpoint = <&du_out_lvds0>;
                };
            };
 
            port@1 {
                reg = <1>;
                lvds0_out: endpoint {
                    remote-endpoint = <&panel_in>;
                };
            };
        };
    };
...