Based on kernel version 6.11
. Page generated on 2024-09-24 08:21 EST
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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 | # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) %YAML 1.2 --- $id: http://devicetree.org/schemas/display/bridge/cdns,mhdp8546.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: Cadence MHDP8546 bridge maintainers: - Swapnil Jakhade <sjakhade@cadence.com> - Yuti Amonkar <yamonkar@cadence.com> properties: compatible: enum: - cdns,mhdp8546 - ti,j721e-mhdp8546 reg: minItems: 1 items: - description: Register block of mhdptx apb registers up to PHY mapped area (AUX_CONFIG_P). The AUX and PMA registers are not part of this range, they are instead included in the associated PHY. - description: Register block for DSS_EDP0_INTG_CFG_VP registers in case of TI J7 SoCs. - description: Register block of mhdptx sapb registers. reg-names: minItems: 1 items: - const: mhdptx - const: j721e-intg - const: mhdptx-sapb clocks: maxItems: 1 description: DP bridge clock, used by the IP to know how to translate a number of clock cycles into a time (which is used to comply with DP standard timings and delays). phys: maxItems: 1 description: phandle to the DisplayPort PHY. phy-names: items: - const: dpphy power-domains: maxItems: 1 interrupts: maxItems: 1 ports: $ref: /schemas/graph.yaml#/properties/ports properties: port@0: $ref: /schemas/graph.yaml#/properties/port description: First input port representing the DP bridge input. port@1: $ref: /schemas/graph.yaml#/properties/port description: Second input port representing the DP bridge input. port@2: $ref: /schemas/graph.yaml#/properties/port description: Third input port representing the DP bridge input. port@3: $ref: /schemas/graph.yaml#/properties/port description: Fourth input port representing the DP bridge input. port@4: $ref: /schemas/graph.yaml#/properties/port description: Output port representing the DP bridge output. required: - port@0 - port@4 allOf: - if: properties: compatible: contains: const: ti,j721e-mhdp8546 then: properties: reg: minItems: 2 maxItems: 3 reg-names: minItems: 2 maxItems: 3 else: properties: reg: minItems: 1 maxItems: 2 reg-names: minItems: 1 maxItems: 2 required: - compatible - clocks - reg - reg-names - phys - phy-names - interrupts - ports additionalProperties: false examples: - | #include <dt-bindings/interrupt-controller/arm-gic.h> bus { #address-cells = <2>; #size-cells = <2>; mhdp: dp-bridge@f0fb000000 { compatible = "cdns,mhdp8546"; reg = <0xf0 0xfb000000 0x0 0x1000000>; reg-names = "mhdptx"; clocks = <&mhdp_clock>; phys = <&dp_phy>; phy-names = "dpphy"; interrupts = <GIC_SPI 614 IRQ_TYPE_LEVEL_HIGH>; ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; dp_bridge_input: endpoint { remote-endpoint = <&xxx_dpi_output>; }; }; port@4 { reg = <4>; dp_bridge_output: endpoint { remote-endpoint = <&xxx_dp_connector_input>; }; }; }; }; }; ... |