Based on kernel version 6.11
. Page generated on 2024-09-24 08:21 EST
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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 | # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2 --- $id: http://devicetree.org/schemas/display/bridge/fsl,imx8qxp-ldb.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: Freescale i.MX8qm/qxp LVDS Display Bridge maintainers: - Liu Ying <victor.liu@nxp.com> description: | The Freescale i.MX8qm/qxp LVDS Display Bridge(LDB) has two channels. The i.MX8qm/qxp LDB is controlled by Control and Status Registers(CSR) module. The CSR module, as a system controller, contains the LDB's configuration registers. For i.MX8qxp LDB, each channel supports up to 24bpp parallel input color format and can map the input to VESA or JEIDA standards. The two channels cannot be used simultaneously, that is to say, the user should pick one of them to use. Two LDB channels from two LDB instances can work together in LDB split mode to support a dual link LVDS display. The channel indexes have to be different. Channel0 outputs odd pixels and channel1 outputs even pixels. For i.MX8qm LDB, each channel additionally supports up to 30bpp parallel input color format. The two channels can be used simultaneously, either in dual mode or split mode. In dual mode, the two channels output identical data. In split mode, channel0 outputs odd pixels and channel1 outputs even pixels. A side note is that i.MX8qm/qxp LDB is officially called pixel mapper in the SoC reference manuals. The pixel mapper uses logic of LDBs embedded in i.MX6qdl/sx SoCs, i.e., it is essentially based on them. To keep the naming consistency, this binding calls it LDB. properties: compatible: enum: - fsl,imx8qm-ldb - fsl,imx8qxp-ldb "#address-cells": const: 1 "#size-cells": const: 0 clocks: items: - description: pixel clock - description: bypass clock clock-names: items: - const: pixel - const: bypass power-domains: maxItems: 1 fsl,companion-ldb: $ref: /schemas/types.yaml#/definitions/phandle description: | A phandle which points to companion LDB which is used in LDB split mode. patternProperties: "^channel@[0-1]$": type: object description: Represents a channel of LDB. properties: "#address-cells": const: 1 "#size-cells": const: 0 reg: description: The channel index. enum: [ 0, 1 ] phys: description: A phandle to the phy module representing the LVDS PHY. maxItems: 1 phy-names: const: lvds_phy port@0: $ref: /schemas/graph.yaml#/properties/port description: Input port of the channel. port@1: $ref: /schemas/graph.yaml#/properties/port description: Output port of the channel. required: - "#address-cells" - "#size-cells" - reg - phys - phy-names additionalProperties: false required: - compatible - "#address-cells" - "#size-cells" - clocks - clock-names - power-domains - channel@0 - channel@1 allOf: - if: properties: compatible: contains: const: fsl,imx8qm-ldb then: properties: fsl,companion-ldb: false additionalProperties: false examples: - | #include <dt-bindings/firmware/imx/rsrc.h> ldb { #address-cells = <1>; #size-cells = <0>; compatible = "fsl,imx8qxp-ldb"; clocks = <&clk IMX_SC_R_LVDS_0 IMX_SC_PM_CLK_MISC2>, <&clk IMX_SC_R_LVDS_0 IMX_SC_PM_CLK_BYPASS>; clock-names = "pixel", "bypass"; power-domains = <&pd IMX_SC_R_LVDS_0>; channel@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; phys = <&mipi_lvds_0_phy>; phy-names = "lvds_phy"; port@0 { reg = <0>; mipi_lvds_0_ldb_ch0_mipi_lvds_0_pxl2dpi: endpoint { remote-endpoint = <&mipi_lvds_0_pxl2dpi_mipi_lvds_0_ldb_ch0>; }; }; }; channel@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; phys = <&mipi_lvds_0_phy>; phy-names = "lvds_phy"; port@0 { reg = <0>; mipi_lvds_0_ldb_ch1_mipi_lvds_0_pxl2dpi: endpoint { remote-endpoint = <&mipi_lvds_0_pxl2dpi_mipi_lvds_0_ldb_ch1>; }; }; }; }; |