Based on kernel version 6.11
. Page generated on 2024-09-24 08:21 EST
.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 | # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause %YAML 1.2 --- $id: http://devicetree.org/schemas/ufs/cdns,ufshc.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: Cadence Universal Flash Storage (UFS) Controller maintainers: - Jan Kotas <jank@cadence.com> # Select only our matches, not all jedec,ufs-2.0 select: properties: compatible: contains: enum: - cdns,ufshc - cdns,ufshc-m31-16nm required: - compatible allOf: - $ref: ufs-common.yaml properties: compatible: items: - enum: - cdns,ufshc # CDNS UFS HC + M31 16nm PHY - cdns,ufshc-m31-16nm - const: jedec,ufs-2.0 clocks: minItems: 1 maxItems: 3 clock-names: minItems: 1 items: - const: core_clk - const: phy_clk - const: ref_clk power-domains: maxItems: 1 reg: maxItems: 1 dma-coherent: true required: - compatible - clocks - clock-names - reg unevaluatedProperties: false examples: - | #include <dt-bindings/interrupt-controller/arm-gic.h> ufs@fd030000 { compatible = "cdns,ufshc", "jedec,ufs-2.0"; reg = <0xfd030000 0x10000>; interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; freq-table-hz = <0 0>, <0 0>; clocks = <&ufs_core_clk>, <&ufs_phy_clk>; clock-names = "core_clk", "phy_clk"; }; |