Based on kernel version 6.10
. Page generated on 2024-07-16 09:00 EST
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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 | # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause %YAML 1.2 --- $id: http://devicetree.org/schemas/perf/arm,coresight-pmu.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: Arm Coresight Performance Monitoring Unit Architecture maintainers: - Robin Murphy <robin.murphy@arm.com> properties: compatible: const: arm,coresight-pmu reg: items: - description: Register page 0 - description: Register page 1, if the PMU implements the dual-page extension minItems: 1 interrupts: items: - description: Overflow interrupt cpus: description: If the PMU is associated with a particular CPU or subset of CPUs, array of phandles to the appropriate CPU node(s) reg-io-width: description: Granularity at which PMU register accesses are single-copy atomic default: 4 enum: [4, 8] required: - compatible - reg additionalProperties: false |