Based on kernel version 6.11
. Page generated on 2024-09-24 08:21 EST
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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 | # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) # Copyright 2020 Arm Ltd. %YAML 1.2 --- $id: http://devicetree.org/schemas/perf/arm,cmn.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: Arm CMN (Coherent Mesh Network) Performance Monitors maintainers: - Robin Murphy <robin.murphy@arm.com> properties: compatible: enum: - arm,cmn-600 - arm,cmn-650 - arm,cmn-700 - arm,ci-700 reg: items: - description: Physical address of the base (PERIPHBASE) and size of the configuration address space. interrupts: minItems: 1 items: - description: Overflow interrupt for DTC0 - description: Overflow interrupt for DTC1 - description: Overflow interrupt for DTC2 - description: Overflow interrupt for DTC3 description: One interrupt for each DTC domain implemented must be specified, in order. DTC0 is always present. arm,root-node: $ref: /schemas/types.yaml#/definitions/uint32 description: Offset from PERIPHBASE of CMN-600's configuration discovery node (see TRM definition of ROOTNODEBASE). Not relevant for newer CMN/CI products. required: - compatible - reg - interrupts if: properties: compatible: contains: const: arm,cmn-600 then: required: - arm,root-node additionalProperties: false examples: - | #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/interrupt-controller/irq.h> pmu@50000000 { compatible = "arm,cmn-600"; reg = <0x50000000 0x4000000>; /* 4x2 mesh with one DTC, and CFG node at 0,1,1,0 */ interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; arm,root-node = <0x104000>; }; ... |