Based on kernel version 6.11
. Page generated on 2024-09-24 08:21 EST
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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 | # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2 --- $id: http://devicetree.org/schemas/iommu/qcom,tbu.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: Qualcomm TBU (Translation Buffer Unit) maintainers: - Georgi Djakov <quic_c_gdjako@quicinc.com> description: The Qualcomm SMMU500 implementation consists of TCU and TBU. The TBU contains a Translation Lookaside Buffer (TLB) that caches page tables. TBUs provides debug features to trace and trigger debug transactions. There are multiple TBU instances with each client core. properties: compatible: enum: - qcom,sc7280-tbu - qcom,sdm845-tbu reg: maxItems: 1 clocks: maxItems: 1 interconnects: maxItems: 1 power-domains: maxItems: 1 qcom,stream-id-range: description: | Phandle of a SMMU device and Stream ID range (address and size) that is assigned by the TBU $ref: /schemas/types.yaml#/definitions/phandle-array items: - items: - description: phandle of a smmu node - description: stream id base address - description: stream id size required: - compatible - reg - qcom,stream-id-range additionalProperties: false examples: - | #include <dt-bindings/clock/qcom,gcc-sdm845.h> #include <dt-bindings/interconnect/qcom,icc.h> #include <dt-bindings/interconnect/qcom,sdm845.h> tbu@150e1000 { compatible = "qcom,sdm845-tbu"; reg = <0x150e1000 0x1000>; clocks = <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>; interconnects = <&system_noc MASTER_GNOC_SNOC QCOM_ICC_TAG_ACTIVE_ONLY &config_noc SLAVE_IMEM_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; power-domains = <&gcc HLOS1_VOTE_AGGRE_NOC_MMU_PCIE_TBU_GDSC>; qcom,stream-id-range = <&apps_smmu 0x1c00 0x400>; }; ... |