Documentation / devicetree / bindings / iommu / nvidia,tegra264-cmdqv.yaml


Based on kernel version 7.0. Page generated on 2026-04-23 09:48 EST.

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/iommu/nvidia,tegra264-cmdqv.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: NVIDIA Tegra264 CMDQV

description:
  The CMDQ-Virtualization hardware block is part of the SMMUv3 implementation
  on Tegra264 SoCs. It assists in virtualizing the command queue for the SMMU.

maintainers:
  - Nicolin Chen <nicolinc@nvidia.com>

properties:
  compatible:
    const: nvidia,tegra264-cmdqv

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

required:
  - compatible
  - reg
  - interrupts

additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/interrupt-controller/irq.h>
 
    cmdqv@5200000 {
            compatible = "nvidia,tegra264-cmdqv";
            reg = <0x5200000 0x830000>;
            interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
    };