Based on kernel version 6.11
. Page generated on 2024-09-24 08:21 EST
.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 | # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2 --- $id: http://devicetree.org/schemas/arm/arm,corstone1000.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: ARM Corstone1000 maintainers: - Vishnu Banavath <vishnu.banavath@arm.com> - Rui Miguel Silva <rui.silva@linaro.org> description: |+ ARM's Corstone1000 includes pre-verified Corstone SSE-710 subsystem that provides a flexible compute architecture that combines Cortex‑A and Cortex‑M processors. Support for Cortex‑A32, Cortex‑A35 and Cortex‑A53 processors. Two expansion systems for M-Class (or other) processors for adding sensors, connectivity, video, audio and machine learning at the edge System and security IPs to build a secure SoC for a range of rich IoT applications, for example gateways, smart cameras and embedded systems. Integrated Secure Enclave providing hardware Root of Trust and supporting seamless integration of the optional CryptoCell™-312 cryptographic accelerator. properties: $nodename: const: '/' compatible: oneOf: - description: Corstone1000 MPS3 it has 1 Cortex-A35 CPU core in a FPGA implementation of the Corstone1000 in the MPS3 prototyping board. See ARM document DAI0550. items: - const: arm,corstone1000-mps3 - description: Corstone1000 FVP is the Fixed Virtual Platform implementation of this system. See ARM ecosystems FVP's. items: - const: arm,corstone1000-fvp additionalProperties: true ... |