Based on kernel version 6.11
. Page generated on 2024-09-24 08:21 EST
.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 | # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause %YAML 1.2 --- $id: http://devicetree.org/schemas/arm/arm,coresight-tpiu.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: Arm CoreSight Trace Port Interface Unit maintainers: - Mathieu Poirier <mathieu.poirier@linaro.org> - Mike Leach <mike.leach@linaro.org> - Leo Yan <leo.yan@linaro.org> - Suzuki K Poulose <suzuki.poulose@arm.com> description: | CoreSight components are compliant with the ARM CoreSight architecture specification and can be connected in various topologies to suit a particular SoCs tracing needs. These trace components can generally be classified as sinks, links and sources. Trace data produced by one or more sources flows through the intermediate links connecting the source to the currently selected sink. The CoreSight Trace Port Interface Unit captures trace data from the trace bus and outputs it to an external trace port. # Need a custom select here or 'arm,primecell' will match on lots of nodes select: properties: compatible: contains: const: arm,coresight-tpiu required: - compatible allOf: - $ref: /schemas/arm/primecell.yaml# properties: compatible: items: - const: arm,coresight-tpiu - const: arm,primecell reg: maxItems: 1 clocks: minItems: 1 maxItems: 2 clock-names: minItems: 1 items: - const: apb_pclk - const: atclk power-domains: maxItems: 1 in-ports: $ref: /schemas/graph.yaml#/properties/ports additionalProperties: false properties: port: description: Input connection from the CoreSight Trace bus. $ref: /schemas/graph.yaml#/properties/port required: - compatible - reg - clocks - clock-names - in-ports unevaluatedProperties: false examples: - | tpiu@e3c05000 { compatible = "arm,coresight-tpiu", "arm,primecell"; reg = <0xe3c05000 0x1000>; clocks = <&clk_375m>; clock-names = "apb_pclk"; in-ports { port { tpiu_in_port: endpoint { remote-endpoint = <&funnel4_out_port0>; }; }; }; }; ... |