# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/arm,coresight-stm.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Arm CoreSight System Trace MacroCell

maintainers:
  - Mathieu Poirier <mathieu.poirier@linaro.org>
  - Mike Leach <mike.leach@linaro.org>
  - Leo Yan <leo.yan@linaro.org>
  - Suzuki K Poulose <suzuki.poulose@arm.com>

description: |
  CoreSight components are compliant with the ARM CoreSight architecture
  specification and can be connected in various topologies to suit a particular
  SoCs tracing needs. These trace components can generally be classified as
  sinks, links and sources. Trace data produced by one or more sources flows
  through the intermediate links connecting the source to the currently selected
  sink.
 
  The STM is a trace source that is integrated into a CoreSight system, designed
  primarily for high-bandwidth trace of instrumentation embedded into software.
  This instrumentation is made up of memory-mapped writes to the STM Advanced
  eXtensible Interface (AXI) slave, which carry information about the behavior
  of the software.

select:
  properties:
    compatible:
      contains:
        const: arm,coresight-stm
  required:
    - compatible

allOf:
  - $ref: /schemas/arm/primecell.yaml#

properties:
  compatible:
    items:
      - const: arm,coresight-stm
      - const: arm,primecell

  reg:
    maxItems: 2

  reg-names:
    items:
      - const: stm-base
      - const: stm-stimulus-base

  clocks:
    minItems: 1
    maxItems: 2

  clock-names:
    minItems: 1
    items:
      - const: apb_pclk
      - const: atclk

  power-domains:
    maxItems: 1

  out-ports:
    $ref: /schemas/graph.yaml#/properties/ports
    additionalProperties: false

    properties:
      port:
        description: Output connection to the CoreSight Trace bus.
        $ref: /schemas/graph.yaml#/properties/port

required:
  - compatible
  - reg
  - reg-names
  - clocks
  - clock-names
  - out-ports

unevaluatedProperties: false

examples:
  - |
    stm@20100000 {
        compatible = "arm,coresight-stm", "arm,primecell";
        reg = <0x20100000 0x1000>,
              <0x28000000 0x180000>;
        reg-names = "stm-base", "stm-stimulus-base";
 
        clocks = <&soc_smc50mhz>;
        clock-names = "apb_pclk";
        out-ports {
            port {
                stm_out_port: endpoint {
                    remote-endpoint = <&main_funnel_in_port2>;
                };
            };
        };
    };
...