Based on kernel version 6.11
. Page generated on 2024-09-24 08:21 EST
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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 | # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) %YAML 1.2 --- $id: http://devicetree.org/schemas/watchdog/fsl-imx7ulp-wdt.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: Freescale i.MX7ULP Watchdog Timer (WDT) Controller maintainers: - Shawn Guo <shawnguo@kernel.org> - Sascha Hauer <s.hauer@pengutronix.de> - Fabio Estevam <festevam@gmail.com> allOf: - $ref: watchdog.yaml# properties: compatible: oneOf: - const: fsl,imx7ulp-wdt - items: - const: fsl,imx8ulp-wdt - const: fsl,imx7ulp-wdt - const: fsl,imx93-wdt reg: maxItems: 1 interrupts: maxItems: 1 clocks: maxItems: 1 fsl,ext-reset-output: description: When set, wdog can generate external reset from the wdog_any pin. type: boolean required: - compatible - interrupts - reg - clocks unevaluatedProperties: false examples: - | #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/clock/imx7ulp-clock.h> watchdog@403d0000 { compatible = "fsl,imx7ulp-wdt"; reg = <0x403d0000 0x10000>; interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; clocks = <&pcc2 IMX7ULP_CLK_WDG1>; assigned-clocks = <&pcc2 IMX7ULP_CLK_WDG1>; assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC_BUS_CLK>; timeout-sec = <40>; }; ... |