Based on kernel version 6.11
. Page generated on 2024-09-24 08:21 EST
.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 | # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2 --- $id: http://devicetree.org/schemas/power/allwinner,sun20i-d1-ppu.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: Allwinner SoCs PPU power domain controller maintainers: - Samuel Holland <samuel@sholland.org> description: D1 and related SoCs contain a power domain controller for the CPUs, GPU, and video-related hardware. properties: compatible: enum: - allwinner,sun20i-d1-ppu reg: maxItems: 1 clocks: description: Bus Clock maxItems: 1 resets: maxItems: 1 '#power-domain-cells': const: 1 required: - compatible - reg - clocks - resets - '#power-domain-cells' additionalProperties: false examples: - | #include <dt-bindings/clock/sun20i-d1-r-ccu.h> #include <dt-bindings/reset/sun20i-d1-r-ccu.h> ppu: power-controller@7001000 { compatible = "allwinner,sun20i-d1-ppu"; reg = <0x7001000 0x1000>; clocks = <&r_ccu CLK_BUS_R_PPU>; resets = <&r_ccu RST_BUS_R_PPU>; #power-domain-cells = <1>; }; |