Based on kernel version 6.11. Page generated on 2024-09-24 08:21 EST.
| 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400 401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 416 417 418 419 420 421 422 423 424 425 426 427 428 429 430 431 432 433 434 435 436 437 438 439 440 441 442 443 444 445 446 447 448 449 450 451 452 453 454 455 456 457 458 459 460 461 462 463 464 465 466 467 468 469 470 471 472 473 474 475 | # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2 --- $id: http://devicetree.org/schemas/opp/opp-v2.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: Generic OPP (Operating Performance Points) maintainers: - Viresh Kumar <viresh.kumar@linaro.org> allOf: - $ref: opp-v2-base.yaml# properties: compatible: const: operating-points-v2 unevaluatedProperties: false examples: - | /* * Example 1: Single cluster Dual-core ARM cortex A9, switch DVFS states * together. */ cpus { #address-cells = <1>; #size-cells = <0>; cpu@0 { compatible = "arm,cortex-a9"; device_type = "cpu"; reg = <0>; next-level-cache = <&L2>; clocks = <&clk_controller 0>; clock-names = "cpu"; cpu-supply = <&cpu_supply0>; operating-points-v2 = <&cpu0_opp_table0>; }; cpu@1 { compatible = "arm,cortex-a9"; device_type = "cpu"; reg = <1>; next-level-cache = <&L2>; clocks = <&clk_controller 0>; clock-names = "cpu"; cpu-supply = <&cpu_supply0>; operating-points-v2 = <&cpu0_opp_table0>; }; }; cpu0_opp_table0: opp-table { compatible = "operating-points-v2"; opp-shared; opp-1000000000 { opp-hz = /bits/ 64 <1000000000>; opp-microvolt = <975000 970000 985000>; opp-microamp = <70000>; clock-latency-ns = <300000>; opp-suspend; }; opp-1100000000 { opp-hz = /bits/ 64 <1100000000>; opp-microvolt = <1000000 980000 1010000>; opp-microamp = <80000>; clock-latency-ns = <310000>; }; opp-1200000000 { opp-hz = /bits/ 64 <1200000000>; opp-microvolt = <1025000>; clock-latency-ns = <290000>; turbo-mode; }; }; - | /* * Example 2: Single cluster, Quad-core Qualcom-krait, switches DVFS states * independently. */ cpus { #address-cells = <1>; #size-cells = <0>; cpu@0 { compatible = "qcom,krait"; device_type = "cpu"; reg = <0>; next-level-cache = <&L2>; clocks = <&clk_controller 0>; clock-names = "cpu"; cpu-supply = <&cpu_supply0>; operating-points-v2 = <&cpu_opp_table>; }; cpu@1 { compatible = "qcom,krait"; device_type = "cpu"; reg = <1>; next-level-cache = <&L2>; clocks = <&clk_controller 1>; clock-names = "cpu"; cpu-supply = <&cpu_supply1>; operating-points-v2 = <&cpu_opp_table>; }; cpu@2 { compatible = "qcom,krait"; device_type = "cpu"; reg = <2>; next-level-cache = <&L2>; clocks = <&clk_controller 2>; clock-names = "cpu"; cpu-supply = <&cpu_supply2>; operating-points-v2 = <&cpu_opp_table>; }; cpu@3 { compatible = "qcom,krait"; device_type = "cpu"; reg = <3>; next-level-cache = <&L2>; clocks = <&clk_controller 3>; clock-names = "cpu"; cpu-supply = <&cpu_supply3>; operating-points-v2 = <&cpu_opp_table>; }; }; cpu_opp_table: opp-table { compatible = "operating-points-v2"; /* * Missing opp-shared property means CPUs switch DVFS states * independently. */ opp-1000000000 { opp-hz = /bits/ 64 <1000000000>; opp-microvolt = <975000 970000 985000>; opp-microamp = <70000>; clock-latency-ns = <300000>; opp-suspend; }; opp-1100000000 { opp-hz = /bits/ 64 <1100000000>; opp-microvolt = <1000000 980000 1010000>; opp-microamp = <80000>; clock-latency-ns = <310000>; }; opp-1200000000 { opp-hz = /bits/ 64 <1200000000>; opp-microvolt = <1025000>; opp-microamp = <90000>; clock-latency-ns = <290000>; turbo-mode; }; }; - | /* * Example 3: Dual-cluster, Dual-core per cluster. CPUs within a cluster switch * DVFS state together. */ cpus { #address-cells = <1>; #size-cells = <0>; cpu@0 { compatible = "arm,cortex-a7"; device_type = "cpu"; reg = <0>; next-level-cache = <&L2>; clocks = <&clk_controller 0>; clock-names = "cpu"; cpu-supply = <&cpu_supply0>; operating-points-v2 = <&cluster0_opp>; }; cpu@1 { compatible = "arm,cortex-a7"; device_type = "cpu"; reg = <1>; next-level-cache = <&L2>; clocks = <&clk_controller 0>; clock-names = "cpu"; cpu-supply = <&cpu_supply0>; operating-points-v2 = <&cluster0_opp>; }; cpu@100 { compatible = "arm,cortex-a15"; device_type = "cpu"; reg = <100>; next-level-cache = <&L2>; clocks = <&clk_controller 1>; clock-names = "cpu"; cpu-supply = <&cpu_supply1>; operating-points-v2 = <&cluster1_opp>; }; cpu@101 { compatible = "arm,cortex-a15"; device_type = "cpu"; reg = <101>; next-level-cache = <&L2>; clocks = <&clk_controller 1>; clock-names = "cpu"; cpu-supply = <&cpu_supply1>; operating-points-v2 = <&cluster1_opp>; }; }; cluster0_opp: opp-table-0 { compatible = "operating-points-v2"; opp-shared; opp-1000000000 { opp-hz = /bits/ 64 <1000000000>; opp-microvolt = <975000 970000 985000>; opp-microamp = <70000>; clock-latency-ns = <300000>; opp-suspend; }; opp-1100000000 { opp-hz = /bits/ 64 <1100000000>; opp-microvolt = <1000000 980000 1010000>; opp-microamp = <80000>; clock-latency-ns = <310000>; }; opp-1200000000 { opp-hz = /bits/ 64 <1200000000>; opp-microvolt = <1025000>; opp-microamp = <90000>; clock-latency-ns = <290000>; turbo-mode; }; }; cluster1_opp: opp-table-1 { compatible = "operating-points-v2"; opp-shared; opp-1300000000 { opp-hz = /bits/ 64 <1300000000>; opp-microvolt = <1050000 1045000 1055000>; opp-microamp = <95000>; clock-latency-ns = <400000>; opp-suspend; }; opp-1400000000 { opp-hz = /bits/ 64 <1400000000>; opp-microvolt = <1075000>; opp-microamp = <100000>; clock-latency-ns = <400000>; }; opp-1500000000 { opp-hz = /bits/ 64 <1500000000>; opp-microvolt = <1100000 1010000 1110000>; opp-microamp = <95000>; clock-latency-ns = <400000>; turbo-mode; }; }; - | /* Example 4: Handling multiple regulators */ cpus { #address-cells = <1>; #size-cells = <0>; cpu@0 { compatible = "foo,cpu-type"; device_type = "cpu"; reg = <0>; vcc0-supply = <&cpu_supply0>; vcc1-supply = <&cpu_supply1>; vcc2-supply = <&cpu_supply2>; operating-points-v2 = <&cpu0_opp_table4>; }; }; cpu0_opp_table4: opp-table-0 { compatible = "operating-points-v2"; opp-shared; opp-1000000000 { opp-hz = /bits/ 64 <1000000000>; opp-microvolt = <970000>, /* Supply 0 */ <960000>, /* Supply 1 */ <960000>; /* Supply 2 */ opp-microamp = <70000>, /* Supply 0 */ <70000>, /* Supply 1 */ <70000>; /* Supply 2 */ clock-latency-ns = <300000>; }; /* OR */ opp-1000000001 { opp-hz = /bits/ 64 <1000000001>; opp-microvolt = <975000 970000 985000>, /* Supply 0 */ <965000 960000 975000>, /* Supply 1 */ <965000 960000 975000>; /* Supply 2 */ opp-microamp = <70000>, /* Supply 0 */ <70000>, /* Supply 1 */ <70000>; /* Supply 2 */ clock-latency-ns = <300000>; }; /* OR */ opp-1000000002 { opp-hz = /bits/ 64 <1000000002>; opp-microvolt = <975000 970000 985000>, /* Supply 0 */ <965000 960000 975000>, /* Supply 1 */ <965000 960000 975000>; /* Supply 2 */ opp-microamp = <70000>, /* Supply 0 */ <0>, /* Supply 1 doesn't need this */ <70000>; /* Supply 2 */ clock-latency-ns = <300000>; }; }; - | /* * Example 5: opp-supported-hw * (example: three level hierarchy of versions: cuts, substrate and process) */ cpus { #address-cells = <1>; #size-cells = <0>; cpu@0 { compatible = "arm,cortex-a7"; device_type = "cpu"; reg = <0>; cpu-supply = <&cpu_supply>; operating-points-v2 = <&cpu0_opp_table_slow>; }; }; cpu0_opp_table_slow: opp-table { compatible = "operating-points-v2"; opp-shared; opp-600000000 { /* * Supports all substrate and process versions for 0xF * cuts, i.e. only first four cuts. */ opp-supported-hw = <0xF 0xFFFFFFFF 0xFFFFFFFF>; opp-hz = /bits/ 64 <600000000>; }; opp-800000000 { /* * Supports: * - cuts: only one, 6th cut (represented by 6th bit). * - substrate: supports 16 different substrate versions * - process: supports 9 different process versions */ opp-supported-hw = <0x20 0xff0000ff 0x0000f4f0>; opp-hz = /bits/ 64 <800000000>; }; opp-900000000 { /* * Supports: * - All cuts and substrate where process version is 0x2. * - All cuts and process where substrate version is 0x2. */ opp-supported-hw = <0xFFFFFFFF 0xFFFFFFFF 0x02>, <0xFFFFFFFF 0x01 0xFFFFFFFF>; opp-hz = /bits/ 64 <900000000>; }; }; - | /* * Example 6: opp-microvolt-<name>, opp-microamp-<name>: * (example: device with two possible microvolt ranges: slow and fast) */ cpus { #address-cells = <1>; #size-cells = <0>; cpu@0 { compatible = "arm,cortex-a7"; device_type = "cpu"; reg = <0>; operating-points-v2 = <&cpu0_opp_table6>; }; }; cpu0_opp_table6: opp-table-0 { compatible = "operating-points-v2"; opp-shared; opp-1000000000 { opp-hz = /bits/ 64 <1000000000>; opp-microvolt-slow = <915000 900000 925000>; opp-microvolt-fast = <975000 970000 985000>; opp-microamp-slow = <70000>; opp-microamp-fast = <71000>; }; opp-1200000000 { opp-hz = /bits/ 64 <1200000000>; opp-microvolt-slow = <915000 900000 925000>, /* Supply vcc0 */ <925000 910000 935000>; /* Supply vcc1 */ opp-microvolt-fast = <975000 970000 985000>, /* Supply vcc0 */ <965000 960000 975000>; /* Supply vcc1 */ opp-microamp = <70000>; /* Will be used for both slow/fast */ }; }; - | /* * Example 7: Single cluster Quad-core ARM cortex A53, OPP points from firmware, * distinct clock controls but two sets of clock/voltage/current lines. */ cpus { #address-cells = <2>; #size-cells = <0>; cpu@0 { compatible = "arm,cortex-a53"; device_type = "cpu"; reg = <0x0 0x100>; next-level-cache = <&A53_L2>; clocks = <&dvfs_controller 0>; operating-points-v2 = <&cpu_opp0_table>; }; cpu@1 { compatible = "arm,cortex-a53"; device_type = "cpu"; reg = <0x0 0x101>; next-level-cache = <&A53_L2>; clocks = <&dvfs_controller 1>; operating-points-v2 = <&cpu_opp0_table>; }; cpu@2 { compatible = "arm,cortex-a53"; device_type = "cpu"; reg = <0x0 0x102>; next-level-cache = <&A53_L2>; clocks = <&dvfs_controller 2>; operating-points-v2 = <&cpu_opp1_table>; }; cpu@3 { compatible = "arm,cortex-a53"; device_type = "cpu"; reg = <0x0 0x103>; next-level-cache = <&A53_L2>; clocks = <&dvfs_controller 3>; operating-points-v2 = <&cpu_opp1_table>; }; }; cpu_opp0_table: opp-table-0 { compatible = "operating-points-v2"; opp-shared; }; cpu_opp1_table: opp-table-1 { compatible = "operating-points-v2"; opp-shared; }; ... |