Based on kernel version 6.11
. Page generated on 2024-09-24 08:21 EST
.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 | # SPDX-License-Identifier: GPL-2.0 %YAML 1.2 --- $id: http://devicetree.org/schemas/opp/allwinner,sun50i-h6-operating-points.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: Allwinner H6 CPU OPP maintainers: - Chen-Yu Tsai <wens@csie.org> - Maxime Ripard <mripard@kernel.org> description: | For some SoCs, the CPU frequency subset and voltage value of each OPP varies based on the silicon variant in use. Allwinner Process Voltage Scaling Tables define the voltage and frequency values based on the speedbin blown in the efuse combination. allOf: - $ref: opp-v2-base.yaml# properties: compatible: enum: - allwinner,sun50i-h6-operating-points - allwinner,sun50i-h616-operating-points nvmem-cells: description: | A phandle pointing to a nvmem-cells node representing the efuse register that has information about the speedbin that is used to select the right frequency/voltage value pair. Please refer to the nvmem-cells bindings in Documentation/devicetree/bindings/nvmem/nvmem.yaml and also the examples below. opp-shared: true required: - compatible - nvmem-cells patternProperties: "^opp-[0-9]+$": type: object properties: opp-hz: true clock-latency-ns: true opp-microvolt: true opp-supported-hw: maxItems: 1 description: A single 32 bit bitmap value, representing compatible HW, one bit per speed bin index. patternProperties: "^opp-microvolt-speed[0-9]$": true required: - opp-hz unevaluatedProperties: false additionalProperties: false examples: - | cpu_opp_table: opp-table { compatible = "allwinner,sun50i-h6-operating-points"; nvmem-cells = <&speedbin_efuse>; opp-shared; opp-480000000 { clock-latency-ns = <244144>; /* 8 32k periods */ opp-hz = /bits/ 64 <480000000>; opp-microvolt-speed0 = <880000>; opp-microvolt-speed1 = <820000>; opp-microvolt-speed2 = <800000>; }; opp-1080000000 { clock-latency-ns = <244144>; /* 8 32k periods */ opp-hz = /bits/ 64 <1080000000>; opp-microvolt-speed0 = <1060000>; opp-microvolt-speed1 = <880000>; opp-microvolt-speed2 = <840000>; }; opp-1488000000 { clock-latency-ns = <244144>; /* 8 32k periods */ opp-hz = /bits/ 64 <1488000000>; opp-microvolt-speed0 = <1160000>; opp-microvolt-speed1 = <1000000>; opp-microvolt-speed2 = <960000>; }; }; - | opp-table { compatible = "allwinner,sun50i-h616-operating-points"; nvmem-cells = <&speedbin_efuse>; opp-shared; opp-480000000 { clock-latency-ns = <244144>; /* 8 32k periods */ opp-hz = /bits/ 64 <480000000>; opp-microvolt = <900000>; opp-supported-hw = <0x1f>; }; opp-792000000 { clock-latency-ns = <244144>; /* 8 32k periods */ opp-hz = /bits/ 64 <792000000>; opp-microvolt-speed1 = <900000>; opp-microvolt-speed4 = <940000>; opp-supported-hw = <0x12>; }; opp-1512000000 { clock-latency-ns = <244144>; /* 8 32k periods */ opp-hz = /bits/ 64 <1512000000>; opp-microvolt = <1100000>; opp-supported-hw = <0x0a>; }; }; ... |