Based on kernel version 6.11. Page generated on 2024-09-24 08:21 EST.
| 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 | # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2 --- $id: http://devicetree.org/schemas/opp/opp-v2-kryo-cpu.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: Qualcomm Technologies, Inc. NVMEM OPP maintainers: - Ilia Lin <ilia.lin@kernel.org> allOf: - $ref: opp-v2-base.yaml# description: | In certain Qualcomm Technologies, Inc. SoCs like APQ8096 and MSM8996, the CPU frequencies subset and voltage value of each OPP varies based on the silicon variant in use. Qualcomm Technologies, Inc. Process Voltage Scaling Tables defines the voltage and frequency value based on the speedbin blown in the efuse combination. The qcom-cpufreq-nvmem driver reads the efuse value from the SoC to provide the OPP framework with required information (existing HW bitmap). This is used to determine the voltage and frequency value for each OPP of operating-points-v2 table when it is parsed by the OPP framework. properties: compatible: enum: - operating-points-v2-krait-cpu - operating-points-v2-kryo-cpu nvmem-cells: description: | A phandle pointing to a nvmem-cells node representing the efuse registers that has information about the speedbin that is used to select the right frequency/voltage value pair. opp-shared: true patternProperties: '^opp-?[0-9]+$': type: object additionalProperties: false properties: opp-hz: true opp-microvolt: true opp-peak-kBps: true opp-supported-hw: description: | A single 32 bit bitmap value, representing compatible HW. Bitmap for MSM8996 format: 0: MSM8996, speedbin 0 1: MSM8996, speedbin 1 2: MSM8996, speedbin 2 3: MSM8996, speedbin 3 4-31: unused Bitmap for MSM8996SG format (speedbin shifted of 4 left): 0-3: unused 4: MSM8996SG, speedbin 0 5: MSM8996SG, speedbin 1 6: MSM8996SG, speedbin 2 7-31: unused Bitmap for IPQ806x SoC: 0: IPQ8062 1: IPQ8064/IPQ8066/IPQ8068 2: IPQ8065/IPQ8069 3-31: unused Other platforms use bits directly corresponding to speedbin index. clock-latency-ns: true required-opps: true patternProperties: '^opp-microvolt-speed[0-9]+-pvs[0-9]+$': true required: - opp-hz required: - compatible if: required: - nvmem-cells then: patternProperties: '^opp-?[0-9]+$': required: - opp-supported-hw additionalProperties: false examples: - | / { model = "Qualcomm Technologies, Inc. DB820c"; compatible = "arrow,apq8096-db820c", "qcom,apq8096-sbc", "qcom,apq8096"; #address-cells = <2>; #size-cells = <2>; cpus { #address-cells = <2>; #size-cells = <0>; CPU0: cpu@0 { device_type = "cpu"; compatible = "qcom,kryo"; reg = <0x0 0x0>; enable-method = "psci"; cpu-idle-states = <&CPU_SLEEP_0>; capacity-dmips-mhz = <1024>; clocks = <&kryocc 0>; operating-points-v2 = <&cluster0_opp>; power-domains = <&cpr>; power-domain-names = "cpr"; #cooling-cells = <2>; next-level-cache = <&L2_0>; L2_0: l2-cache { compatible = "cache"; cache-level = <2>; cache-unified; }; }; CPU1: cpu@1 { device_type = "cpu"; compatible = "qcom,kryo"; reg = <0x0 0x1>; enable-method = "psci"; cpu-idle-states = <&CPU_SLEEP_0>; capacity-dmips-mhz = <1024>; clocks = <&kryocc 0>; operating-points-v2 = <&cluster0_opp>; power-domains = <&cpr>; power-domain-names = "cpr"; #cooling-cells = <2>; next-level-cache = <&L2_0>; }; CPU2: cpu@100 { device_type = "cpu"; compatible = "qcom,kryo"; reg = <0x0 0x100>; enable-method = "psci"; cpu-idle-states = <&CPU_SLEEP_0>; capacity-dmips-mhz = <1024>; clocks = <&kryocc 1>; operating-points-v2 = <&cluster1_opp>; power-domains = <&cpr>; power-domain-names = "cpr"; #cooling-cells = <2>; next-level-cache = <&L2_1>; L2_1: l2-cache { compatible = "cache"; cache-level = <2>; cache-unified; }; }; CPU3: cpu@101 { device_type = "cpu"; compatible = "qcom,kryo"; reg = <0x0 0x101>; enable-method = "psci"; cpu-idle-states = <&CPU_SLEEP_0>; capacity-dmips-mhz = <1024>; clocks = <&kryocc 1>; operating-points-v2 = <&cluster1_opp>; power-domains = <&cpr>; power-domain-names = "cpr"; #cooling-cells = <2>; next-level-cache = <&L2_1>; }; cpu-map { cluster0 { core0 { cpu = <&CPU0>; }; core1 { cpu = <&CPU1>; }; }; cluster1 { core0 { cpu = <&CPU2>; }; core1 { cpu = <&CPU3>; }; }; }; }; cluster0_opp: opp-table-0 { compatible = "operating-points-v2-kryo-cpu"; nvmem-cells = <&speedbin_efuse>; opp-shared; opp-307200000 { opp-hz = /bits/ 64 <307200000>; opp-microvolt = <905000 905000 1140000>; opp-supported-hw = <0x7>; clock-latency-ns = <200000>; required-opps = <&cpr_opp1>; }; opp-1401600000 { opp-hz = /bits/ 64 <1401600000>; opp-microvolt = <1140000 905000 1140000>; opp-supported-hw = <0x5>; clock-latency-ns = <200000>; required-opps = <&cpr_opp2>; }; opp-1593600000 { opp-hz = /bits/ 64 <1593600000>; opp-microvolt = <1140000 905000 1140000>; opp-supported-hw = <0x1>; clock-latency-ns = <200000>; required-opps = <&cpr_opp3>; }; }; cluster1_opp: opp-table-1 { compatible = "operating-points-v2-kryo-cpu"; nvmem-cells = <&speedbin_efuse>; opp-shared; opp-307200000 { opp-hz = /bits/ 64 <307200000>; opp-microvolt = <905000 905000 1140000>; opp-supported-hw = <0x7>; clock-latency-ns = <200000>; required-opps = <&cpr_opp1>; }; opp-1804800000 { opp-hz = /bits/ 64 <1804800000>; opp-microvolt = <1140000 905000 1140000>; opp-supported-hw = <0x6>; clock-latency-ns = <200000>; required-opps = <&cpr_opp4>; }; opp-1900800000 { opp-hz = /bits/ 64 <1900800000>; opp-microvolt = <1140000 905000 1140000>; opp-supported-hw = <0x4>; clock-latency-ns = <200000>; required-opps = <&cpr_opp5>; }; opp-2150400000 { opp-hz = /bits/ 64 <2150400000>; opp-microvolt = <1140000 905000 1140000>; opp-supported-hw = <0x1>; clock-latency-ns = <200000>; required-opps = <&cpr_opp6>; }; }; /* Dummy opp table to give example for named opp-microvolt */ opp-table-2 { compatible = "operating-points-v2-krait-cpu"; nvmem-cells = <&speedbin_efuse>; opp-384000000 { opp-hz = /bits/ 64 <384000000>; opp-microvolt-speed0-pvs0 = <1000000 950000 1050000>; opp-microvolt-speed0-pvs1 = <925000 878750 971250>; opp-microvolt-speed0-pvs2 = <875000 831250 918750>; opp-microvolt-speed0-pvs3 = <800000 760000 840000>; opp-supported-hw = <0x7>; clock-latency-ns = <100000>; }; }; smem { compatible = "qcom,smem"; memory-region = <&smem_mem>; hwlocks = <&tcsr_mutex 3>; }; soc { #address-cells = <1>; #size-cells = <1>; qfprom: qfprom@74000 { compatible = "qcom,msm8996-qfprom", "qcom,qfprom"; reg = <0x00074000 0x8ff>; #address-cells = <1>; #size-cells = <1>; speedbin_efuse: speedbin@133 { reg = <0x133 0x1>; bits = <5 3>; }; }; }; }; |