Based on kernel version 6.18. Page generated on 2025-12-02 09:03 EST.
| 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 | # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause %YAML 1.2 --- $id: http://devicetree.org/schemas/mailbox/mediatek,mt8196-gpueb-mbox.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: MediaTek MFlexGraphics GPUEB Mailbox Controller maintainers: - Nicolas Frattaroli <nicolas.frattaroli@collabora.com> properties: compatible: enum: - mediatek,mt8196-gpueb-mbox reg: items: - description: mailbox data registers - description: mailbox control registers reg-names: items: - const: data - const: ctl clocks: items: - description: main clock of the GPUEB MCU interrupts: items: - description: fires when a new message is received "#mbox-cells": const: 1 description: The number of the mailbox channel. required: - compatible - reg - reg-names - clocks - interrupts - "#mbox-cells" additionalProperties: false examples: - | #include <dt-bindings/clock/mediatek,mt8196-clock.h> #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/interrupt-controller/irq.h> mailbox@4b09fd80 { compatible = "mediatek,mt8196-gpueb-mbox"; reg = <0x4b09fd80 0x280>, <0x4b170000 0x7c>; reg-names = "data", "ctl"; clocks = <&topckgen CLK_TOP_MFG_EB>; interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH 0>; #mbox-cells = <1>; }; |