Based on kernel version 6.8. Page generated on 2024-03-11 21:26 EST.
| 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 | # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2 --- $id: http://devicetree.org/schemas/display/panel/panel-timing.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: panel timing maintainers: - Thierry Reding <thierry.reding@gmail.com> - Sam Ravnborg <sam@ravnborg.org> description: | There are different ways of describing the timing data of a panel. The devicetree representation corresponds to the one commonly found in datasheets for panels. The parameters are defined as seen in the following illustration. +-------+----------+-------------------------------------+----------+ | | | ^ | | | | | |vsync_len | | | | | v | | +-------+----------+-------------------------------------+----------+ | | | ^ | | | | | |vback_porch | | | | | v | | +-------+----------#######################################----------+ | | # ^ # | | | # | # | | hsync | hback # | # hfront | | len | porch # | hactive # porch | |<----->|<-------->#<-------+--------------------------->#<-------->| | | # | # | | | # |vactive # | | | # | # | | | # v # | +-------+----------#######################################----------+ | | | ^ | | | | | |vfront_porch | | | | | v | | +-------+----------+-------------------------------------+----------+ The following is the panel timings shown with time on the x-axis. This matches the timing diagrams often found in data sheets. Active Front Sync Back Region Porch Porch <-----------------------><----------------><-------------><--------------> //////////////////////| ////////////////////// | ////////////////////// |.................. ................ _______________ Timing can be specified either as a typical value or as a tuple of min, typ, max values. properties: clock-frequency: description: Panel clock in Hz hactive: $ref: /schemas/types.yaml#/definitions/uint32 description: Horizontal panel resolution in pixels vactive: $ref: /schemas/types.yaml#/definitions/uint32 description: Vertical panel resolution in pixels hfront-porch: description: Horizontal front porch panel timing $ref: /schemas/types.yaml#/definitions/uint32-array oneOf: - maxItems: 1 items: description: typical number of pixels - minItems: 3 maxItems: 3 items: description: min, typ, max number of pixels hback-porch: description: Horizontal back porch timing $ref: /schemas/types.yaml#/definitions/uint32-array oneOf: - maxItems: 1 items: description: typical number of pixels - minItems: 3 maxItems: 3 items: description: min, typ, max number of pixels hsync-len: description: Horizontal sync length panel timing $ref: /schemas/types.yaml#/definitions/uint32-array oneOf: - maxItems: 1 items: description: typical number of pixels - minItems: 3 maxItems: 3 items: description: min, typ, max number of pixels vfront-porch: description: Vertical front porch panel timing $ref: /schemas/types.yaml#/definitions/uint32-array oneOf: - maxItems: 1 items: description: typical number of lines - minItems: 3 maxItems: 3 items: description: min, typ, max number of lines vback-porch: description: Vertical back porch panel timing $ref: /schemas/types.yaml#/definitions/uint32-array oneOf: - maxItems: 1 items: description: typical number of lines - minItems: 3 maxItems: 3 items: description: min, typ, max number of lines vsync-len: description: Vertical sync length panel timing $ref: /schemas/types.yaml#/definitions/uint32-array oneOf: - maxItems: 1 items: description: typical number of lines - minItems: 3 maxItems: 3 items: description: min, typ, max number of lines hsync-active: description: | Horizontal sync pulse. 0 selects active low, 1 selects active high. If omitted then it is not used by the hardware $ref: /schemas/types.yaml#/definitions/uint32 enum: [0, 1] vsync-active: description: | Vertical sync pulse. 0 selects active low, 1 selects active high. If omitted then it is not used by the hardware $ref: /schemas/types.yaml#/definitions/uint32 enum: [0, 1] de-active: description: | Data enable. 0 selects active low, 1 selects active high. If omitted then it is not used by the hardware $ref: /schemas/types.yaml#/definitions/uint32 enum: [0, 1] pixelclk-active: description: | Data driving on rising or falling edge. Use 0 to drive pixel data on falling edge and sample data on rising edge. Use 1 to drive pixel data on rising edge and sample data on falling edge $ref: /schemas/types.yaml#/definitions/uint32 enum: [0, 1] syncclk-active: description: | Drive sync on rising or sample sync on falling edge. If not specified then the setup is as specified by pixelclk-active. Use 0 to drive sync on falling edge and sample sync on rising edge of pixel clock. Use 1 to drive sync on rising edge and sample sync on falling edge of pixel clock $ref: /schemas/types.yaml#/definitions/uint32 enum: [0, 1] interlaced: type: boolean description: Enable interlaced mode doublescan: type: boolean description: Enable double scan mode doubleclk: type: boolean description: Enable double clock mode required: - clock-frequency - hactive - vactive - hfront-porch - hback-porch - hsync-len - vfront-porch - vback-porch - vsync-len additionalProperties: false ... |