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Documentation / i2c / busses / i2c-mlxcpld


Based on kernel version 4.16.1. Page generated on 2018-04-09 11:53 EST.

1	Driver i2c-mlxcpld
2	
3	Author: Michael Shych <michaelsh@mellanox.com>
4	
5	This is the Mellanox I2C controller logic, implemented in Lattice CPLD
6	device.
7	Device supports:
8	 - Master mode.
9	 - One physical bus.
10	 - Polling mode.
11	
12	This controller is equipped within the next Mellanox systems:
13	"msx6710", "msx6720", "msb7700", "msn2700", "msx1410", "msn2410", "msb7800",
14	"msn2740", "msn2100".
15	
16	The next transaction types are supported:
17	 - Receive Byte/Block.
18	 - Send Byte/Block.
19	 - Read Byte/Block.
20	 - Write Byte/Block.
21	
22	Registers:
23	CTRL		0x1 - control reg.
24				Resets all the registers.
25	HALF_CYC	0x4 - cycle reg.
26				Configure the width of I2C SCL half clock cycle (in 4 LPC_CLK
27				units).
28	I2C_HOLD	0x5 - hold reg.
29				OE (output enable) is delayed by value set to this register
30				(in LPC_CLK units)
31	CMD			0x6 - command reg.
32				Bit 0, 0 = write, 1 = read.
33				Bits [7:1] - the 7bit Address of the I2C device.
34				It should be written last as it triggers an I2C transaction.
35	NUM_DATA	0x7 - data size reg.
36				Number of data bytes to write in read transaction
37	NUM_ADDR	0x8 - address reg.
38				Number of address bytes to write in read transaction.
39	STATUS		0x9 - status reg.
40				Bit 0 - transaction is completed.
41				Bit 4 - ACK/NACK.
42	DATAx		0xa - 0x54  - 68 bytes data buffer regs.
43				For write transaction address is specified in four first bytes
44				(DATA1 - DATA4), data starting from DATA4.
45				For read transactions address is sent in a separate transaction and
46				specified in the four first bytes (DATA0 - DATA3). Data is read
47				starting from DATA0.
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