# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/soc/qcom/qcom,sa8255p-geni-se-qup.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: GENI Serial Engine QUP Wrapper Controller

maintainers:
  - Praveen Talari <quic_ptalari@quicinc.com>

description:
  Generic Interface (GENI) based Qualcomm Universal Peripheral (QUP) wrapper
  is a programmable module for supporting a wide range of serial interfaces
  like UART, SPI, I2C, I3C, etc. A single QUP module can provide up to 8 Serial
  Interfaces, using its internal Serial Engines. The GENI Serial Engine QUP
  Wrapper controller is modeled as a node with zero or more child nodes each
  representing a serial engine.

properties:
  compatible:
    const: qcom,sa8255p-geni-se-qup

  reg:
    description: QUP wrapper common register address and length.
    maxItems: 1
 
  "#address-cells":
    const: 2
 
  "#size-cells":
    const: 2

  ranges: true

  iommus:
    maxItems: 1

  dma-coherent: true

patternProperties:
  "spi@[0-9a-f]+$":
    type: object
    description: GENI serial engine based SPI controller. SPI in master mode
                 supports up to 50MHz, up to four chip selects, programmable
                 data path from 4 bits to 32 bits and numerous protocol
                 variants.
    additionalProperties: true

    properties:
      compatible:
        const: qcom,sa8255p-geni-spi

  "i2c@[0-9a-f]+$":
    type: object
    description: GENI serial engine based I2C controller.
    additionalProperties: true

    properties:
      compatible:
        const: qcom,sa8255p-geni-i2c

  "serial@[0-9a-f]+$":
    type: object
    description: GENI Serial Engine based UART Controller.
    additionalProperties: true

    properties:
      compatible:
        enum:
          - qcom,sa8255p-geni-uart
          - qcom,sa8255p-geni-debug-uart

required:
  - compatible
  - reg
  - "#address-cells"
  - "#size-cells"
  - ranges

additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>
 
    soc {
        #address-cells = <2>;
        #size-cells = <2>;
 
        geniqup@9c0000 {
            compatible = "qcom,sa8255p-geni-se-qup";
            reg = <0 0x9c0000 0 0x6000>;
            #address-cells = <2>;
            #size-cells = <2>;
            ranges;
 
            serial@990000 {
                compatible = "qcom,sa8255p-geni-uart";
                reg = <0 0x990000 0 0x4000>;
                interrupts = <GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH>;
                power-domains = <&scmi0_pd 0>, <&scmi0_dvfs 0>;
                power-domain-names = "power", "perf";
            };
        };
    };
...