Based on kernel version 6.13
. Page generated on 2025-01-21 08:20 EST
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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 | # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2 --- $id: http://devicetree.org/schemas/memory-controllers/fsl/mmdc.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: Freescale Multi Mode DDR controller (MMDC) maintainers: - Shawn Guo <shawnguo@kernel.org> - Sascha Hauer <s.hauer@pengutronix.de> - Fabio Estevam <festevam@gmail.com> properties: compatible: oneOf: - const: fsl,imx6q-mmdc - items: - enum: - fsl,imx6qp-mmdc - fsl,imx6sl-mmdc - fsl,imx6sll-mmdc - fsl,imx6sx-mmdc - fsl,imx6ul-mmdc - fsl,imx7ulp-mmdc - const: fsl,imx6q-mmdc reg: maxItems: 1 clocks: maxItems: 1 required: - compatible - reg additionalProperties: false examples: - | #include <dt-bindings/clock/imx6qdl-clock.h> memory-controller@21b0000 { compatible = "fsl,imx6q-mmdc"; reg = <0x021b0000 0x4000>; clocks = <&clks IMX6QDL_CLK_MMDC_P0_IPG>; }; memory-controller@21b4000 { compatible = "fsl,imx6q-mmdc"; reg = <0x021b4000 0x4000>; }; |