Based on kernel version 6.16
. Page generated on 2025-08-06 08:57 EST
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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 | # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause %YAML 1.2 --- $id: http://devicetree.org/schemas/display/rockchip/rockchip,rk3399-cdn-dp.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: Rockchip RK3399 specific extensions to the CDN Display Port maintainers: - Andy Yan <andy.yan@rock-chip.com> - Heiko Stuebner <heiko@sntech.de> - Sandy Huang <hjc@rock-chips.com> allOf: - $ref: /schemas/sound/dai-common.yaml# properties: compatible: items: - const: rockchip,rk3399-cdn-dp reg: maxItems: 1 clocks: items: - description: DP core work clock - description: APB clock - description: SPDIF interface clock - description: GRF clock clock-names: items: - const: core-clk - const: pclk - const: spdif - const: grf extcon: $ref: /schemas/types.yaml#/definitions/phandle-array minItems: 1 items: - description: Extcon device providing the cable state for DP PHY device 0 - description: Extcon device providing the cable state for DP PHY device 1 description: List of phandle to the extcon device providing the cable state for the DP PHY. interrupts: maxItems: 1 phys: minItems: 1 items: - description: DP output to the DP PHY device 0 - description: DP output to the DP PHY device 1 description: RK3399 have two DP-USB PHY, specifying one PHY which want to use, or specify two PHYs here to let the driver determine which PHY to use. ports: $ref: /schemas/graph.yaml#/properties/ports properties: port@0: $ref: /schemas/graph.yaml#/properties/port description: Input of the CDN DP properties: endpoint@0: description: Connection to the VOPB endpoint@1: description: Connection to the VOPL port@1: $ref: /schemas/graph.yaml#/properties/port description: Output of the CDN DP required: - port@0 - port@1 power-domains: maxItems: 1 resets: maxItems: 4 reset-names: items: - const: spdif - const: dptx - const: apb - const: core rockchip,grf: $ref: /schemas/types.yaml#/definitions/phandle description: Phandle to GRF register to control HPD. "#sound-dai-cells": const: 1 required: - compatible - reg - clocks - clock-names - interrupts - phys - ports - resets - reset-names - rockchip,grf - "#sound-dai-cells" unevaluatedProperties: false examples: - | #include <dt-bindings/clock/rk3399-cru.h> #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/power/rk3399-power.h> soc { #address-cells = <2>; #size-cells = <2>; dp@fec00000 { compatible = "rockchip,rk3399-cdn-dp"; reg = <0x0 0xfec00000 0x0 0x100000>; assigned-clocks = <&cru SCLK_DP_CORE>; assigned-clock-rates = <100000000>; interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cru SCLK_DP_CORE>, <&cru PCLK_DP_CTRL>, <&cru SCLK_SPDIF_REC_DPTX>, <&cru PCLK_VIO_GRF>; clock-names = "core-clk", "pclk", "spdif", "grf"; power-domains = <&power RK3399_PD_HDCP>; phys = <&tcphy0_dp>, <&tcphy1_dp>; resets = <&cru SRST_DPTX_SPDIF_REC>, <&cru SRST_P_UPHY0_DPTX>, <&cru SRST_P_UPHY0_APB>, <&cru SRST_DP_CORE>; reset-names = "spdif", "dptx", "apb", "core"; rockchip,grf = <&grf>; #sound-dai-cells = <1>; ports { #address-cells = <1>; #size-cells = <0>; dp_in: port@0 { reg = <0>; #address-cells = <1>; #size-cells = <0>; dp_in_vopb: endpoint@0 { reg = <0>; remote-endpoint = <&vopb_out_dp>; }; dp_in_vopl: endpoint@1 { reg = <1>; remote-endpoint = <&vopl_out_dp>; }; }; dp_out: port@1 { reg = <1>; }; }; }; }; |