Based on kernel version 6.11
. Page generated on 2024-09-24 08:21 EST
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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 | # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2 --- $id: http://devicetree.org/schemas/display/rockchip/rockchip,dw-hdmi.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: Rockchip DWC HDMI TX Encoder maintainers: - Mark Yao <markyao0591@gmail.com> description: | The HDMI transmitter is a Synopsys DesignWare HDMI 1.4 TX controller IP with a companion PHY IP. allOf: - $ref: ../bridge/synopsys,dw-hdmi.yaml# - $ref: /schemas/sound/dai-common.yaml# properties: compatible: enum: - rockchip,rk3228-dw-hdmi - rockchip,rk3288-dw-hdmi - rockchip,rk3328-dw-hdmi - rockchip,rk3399-dw-hdmi - rockchip,rk3568-dw-hdmi reg-io-width: const: 4 avdd-0v9-supply: description: A 0.9V supply that powers up the SoC internal circuitry. The actual pin name varies between the different SoCs and is usually HDMI_TX_AVDD_0V9 or sometimes HDMI_AVDD_1V0. avdd-1v8-supply: description: A 1.8V supply that powers up the SoC internal circuitry. The pin name on the SoC usually is HDMI_TX_AVDD_1V8. clocks: minItems: 2 items: - {} - {} # The next three clocks are all optional, but shall be specified in this # order when present. - description: The HDMI CEC controller main clock - description: Power for GRF IO - description: External clock for some HDMI PHY (old clock name, deprecated) - description: External clock for some HDMI PHY (new name) clock-names: minItems: 2 items: - {} - {} - enum: - cec - grf - vpll - ref - enum: - grf - vpll - ref - enum: - vpll - ref phys: maxItems: 1 description: The HDMI PHY phy-names: const: hdmi pinctrl-names: description: The unwedge pinctrl entry shall drive the DDC SDA line low. This is intended to work around a hardware errata that can cause the DDC I2C bus to be wedged. minItems: 1 items: - const: default - const: unwedge power-domains: maxItems: 1 ports: $ref: /schemas/graph.yaml#/properties/ports properties: port@0: $ref: /schemas/graph.yaml#/properties/port description: Input of the DWC HDMI TX properties: endpoint: description: Connection to the VOP endpoint@0: description: Connection to the VOPB endpoint@1: description: Connection to the VOPL port@1: $ref: /schemas/graph.yaml#/properties/port description: Output of the DWC HDMI TX required: - port@0 - port@1 rockchip,grf: $ref: /schemas/types.yaml#/definitions/phandle description: phandle to the GRF to mux vopl/vopb. "#sound-dai-cells": const: 0 required: - compatible - reg - reg-io-width - clocks - clock-names - interrupts - ports - rockchip,grf unevaluatedProperties: false examples: - | #include <dt-bindings/clock/rk3288-cru.h> #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/interrupt-controller/irq.h> #include <dt-bindings/power/rk3288-power.h> hdmi: hdmi@ff980000 { compatible = "rockchip,rk3288-dw-hdmi"; reg = <0xff980000 0x20000>; reg-io-width = <4>; interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>; clock-names = "iahb", "isfr"; ddc-i2c-bus = <&i2c5>; power-domains = <&power RK3288_PD_VIO>; rockchip,grf = <&grf>; #sound-dai-cells = <0>; ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; #address-cells = <1>; #size-cells = <0>; hdmi_in_vopb: endpoint@0 { reg = <0>; remote-endpoint = <&vopb_out_hdmi>; }; hdmi_in_vopl: endpoint@1 { reg = <1>; remote-endpoint = <&vopl_out_hdmi>; }; }; port@1 { reg = <1>; hdmi_out_con: endpoint { remote-endpoint = <&hdmi_con_in>; }; }; }; }; ... |