Based on kernel version 6.11
. Page generated on 2024-09-24 08:21 EST
.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 | # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2 --- $id: http://devicetree.org/schemas/display/mediatek/mediatek,split.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: Mediatek display split maintainers: - Chun-Kuang Hu <chunkuang.hu@kernel.org> - Philipp Zabel <p.zabel@pengutronix.de> description: | Mediatek display split, namely SPLIT, is used to split stream to two encoders. SPLIT device node must be siblings to the central MMSYS_CONFIG node. For a description of the MMSYS_CONFIG binding, see Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml for details. properties: compatible: oneOf: - enum: - mediatek,mt8173-disp-split - mediatek,mt8195-mdp3-split - items: - const: mediatek,mt6795-disp-split - const: mediatek,mt8173-disp-split reg: maxItems: 1 interrupts: maxItems: 1 power-domains: description: A phandle and PM domain specifier as defined by bindings of the power controller specified by phandle. See Documentation/devicetree/bindings/power/power-domain.yaml for details. mediatek,gce-client-reg: description: The register of display function block to be set by gce. There are 4 arguments, such as gce node, subsys id, offset and register size. The subsys id that is mapping to the register of display function blocks is defined in the gce header include/dt-bindings/gce/<chip>-gce.h of each chips. $ref: /schemas/types.yaml#/definitions/phandle-array items: items: - description: phandle of GCE - description: GCE subsys id - description: register offset - description: register size maxItems: 1 clocks: items: - description: SPLIT Clock required: - compatible - reg - power-domains - clocks allOf: - if: properties: compatible: contains: const: mediatek,mt8195-mdp3-split then: required: - mediatek,gce-client-reg additionalProperties: false examples: - | #include <dt-bindings/clock/mt8173-clk.h> #include <dt-bindings/power/mt8173-power.h> soc { #address-cells = <2>; #size-cells = <2>; split0: split@14018000 { compatible = "mediatek,mt8173-disp-split"; reg = <0 0x14018000 0 0x1000>; power-domains = <&spm MT8173_POWER_DOMAIN_MM>; clocks = <&mmsys CLK_MM_DISP_SPLIT0>; }; }; |