Based on kernel version 6.11
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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 | # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2 --- $id: http://devicetree.org/schemas/display/mediatek/mediatek,hdmi.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: Mediatek HDMI Encoder maintainers: - CK Hu <ck.hu@mediatek.com> - Jitao shi <jitao.shi@mediatek.com> description: | The Mediatek HDMI encoder can generate HDMI 1.4a or MHL 2.0 signals from its parallel input. properties: compatible: enum: - mediatek,mt2701-hdmi - mediatek,mt7623-hdmi - mediatek,mt8167-hdmi - mediatek,mt8173-hdmi reg: maxItems: 1 interrupts: maxItems: 1 clocks: items: - description: Pixel Clock - description: HDMI PLL - description: Bit Clock - description: S/PDIF Clock clock-names: items: - const: pixel - const: pll - const: bclk - const: spdif phys: maxItems: 1 phy-names: items: - const: hdmi mediatek,syscon-hdmi: $ref: /schemas/types.yaml#/definitions/phandle-array items: - items: - description: phandle to system configuration registers - description: register offset in the system configuration registers description: | phandle link and register offset to the system configuration registers. ports: $ref: /schemas/graph.yaml#/properties/ports properties: port@0: $ref: /schemas/graph.yaml#/properties/port description: | Input port node. This port should be connected to a DPI output port. port@1: $ref: /schemas/graph.yaml#/properties/port description: | Output port node. This port should be connected to the input port of a connector node that contains a ddc-i2c-bus property, or to the input port of an attached bridge chip, such as a SlimPort transmitter. required: - port@0 - port@1 required: - compatible - reg - interrupts - clocks - clock-names - phys - phy-names - mediatek,syscon-hdmi - ports additionalProperties: false examples: - | #include <dt-bindings/clock/mt8173-clk.h> #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/interrupt-controller/irq.h> hdmi0: hdmi@14025000 { compatible = "mediatek,mt8173-hdmi"; reg = <0x14025000 0x400>; interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_LOW>; clocks = <&mmsys CLK_MM_HDMI_PIXEL>, <&mmsys CLK_MM_HDMI_PLLCK>, <&mmsys CLK_MM_HDMI_AUDIO>, <&mmsys CLK_MM_HDMI_SPDIF>; clock-names = "pixel", "pll", "bclk", "spdif"; pinctrl-names = "default"; pinctrl-0 = <&hdmi_pin>; phys = <&hdmi_phy>; phy-names = "hdmi"; mediatek,syscon-hdmi = <&mmsys 0x900>; ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; hdmi0_in: endpoint { remote-endpoint = <&dpi0_out>; }; }; port@1 { reg = <1>; hdmi0_out: endpoint { remote-endpoint = <&hdmi_con_in>; }; }; }; }; ... |