Based on kernel version 6.11
. Page generated on 2024-09-24 08:21 EST
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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 | # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2 --- $id: http://devicetree.org/schemas/cpufreq/cpufreq-mediatek-hw.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: MediaTek's CPUFREQ maintainers: - Hector Yuan <hector.yuan@mediatek.com> description: CPUFREQ HW is a hardware engine used by MediaTek SoCs to manage frequency in hardware. It is capable of controlling frequency for multiple clusters. properties: compatible: const: mediatek,cpufreq-hw reg: minItems: 1 maxItems: 2 description: Addresses and sizes for the memory of the HW bases in each frequency domain. Each entry corresponds to a register bank for each frequency domain present. "#performance-domain-cells": description: Number of cells in a performance domain specifier. Set const to 1 here for nodes providing multiple performance domains. const: 1 required: - compatible - reg - "#performance-domain-cells" additionalProperties: false examples: - | cpus { #address-cells = <1>; #size-cells = <0>; cpu0: cpu@0 { device_type = "cpu"; compatible = "arm,cortex-a55"; enable-method = "psci"; performance-domains = <&performance 0>; reg = <0x000>; }; }; /* ... */ soc { #address-cells = <2>; #size-cells = <2>; performance: performance-controller@11bc00 { compatible = "mediatek,cpufreq-hw"; reg = <0 0x0011bc10 0 0x120>, <0 0x0011bd30 0 0x120>; #performance-domain-cells = <1>; }; }; |