Based on kernel version 6.11. Page generated on 2024-09-24 08:21 EST.
| 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 | # SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause) %YAML 1.2 --- $id: http://devicetree.org/schemas/cache/qcom,llcc.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: Last Level Cache Controller maintainers: - Bjorn Andersson <andersson@kernel.org> description: | LLCC (Last Level Cache Controller) provides last level of cache memory in SoC, that can be shared by multiple clients. Clients here are different cores in the SoC, the idea is to minimize the local caches at the clients and migrate to common pool of memory. Cache memory is divided into partitions called slices which are assigned to clients. Clients can query the slice details, activate and deactivate them. properties: compatible: enum: - qcom,qdu1000-llcc - qcom,sa8775p-llcc - qcom,sc7180-llcc - qcom,sc7280-llcc - qcom,sc8180x-llcc - qcom,sc8280xp-llcc - qcom,sdm845-llcc - qcom,sm6350-llcc - qcom,sm7150-llcc - qcom,sm8150-llcc - qcom,sm8250-llcc - qcom,sm8350-llcc - qcom,sm8450-llcc - qcom,sm8550-llcc - qcom,sm8650-llcc - qcom,x1e80100-llcc reg: minItems: 2 maxItems: 9 reg-names: minItems: 2 maxItems: 9 interrupts: maxItems: 1 nvmem-cells: items: - description: Reference to an nvmem node for multi channel DDR nvmem-cell-names: items: - const: multi-chan-ddr required: - compatible - reg - reg-names allOf: - if: properties: compatible: contains: enum: - qcom,sc7180-llcc - qcom,sm6350-llcc then: properties: reg: items: - description: LLCC0 base register region - description: LLCC broadcast base register region reg-names: items: - const: llcc0_base - const: llcc_broadcast_base - if: properties: compatible: contains: enum: - qcom,sa8775p-llcc then: properties: reg: items: - description: LLCC0 base register region - description: LLCC1 base register region - description: LLCC2 base register region - description: LLCC3 base register region - description: LLCC4 base register region - description: LLCC5 base register region - description: LLCC broadcast base register region reg-names: items: - const: llcc0_base - const: llcc1_base - const: llcc2_base - const: llcc3_base - const: llcc4_base - const: llcc5_base - const: llcc_broadcast_base - if: properties: compatible: contains: enum: - qcom,sc7280-llcc then: properties: reg: items: - description: LLCC0 base register region - description: LLCC1 base register region - description: LLCC broadcast base register region reg-names: items: - const: llcc0_base - const: llcc1_base - const: llcc_broadcast_base - if: properties: compatible: contains: enum: - qcom,qdu1000-llcc - qcom,sc8180x-llcc - qcom,sc8280xp-llcc - qcom,x1e80100-llcc then: properties: reg: items: - description: LLCC0 base register region - description: LLCC1 base register region - description: LLCC2 base register region - description: LLCC3 base register region - description: LLCC4 base register region - description: LLCC5 base register region - description: LLCC6 base register region - description: LLCC7 base register region - description: LLCC broadcast base register region reg-names: items: - const: llcc0_base - const: llcc1_base - const: llcc2_base - const: llcc3_base - const: llcc4_base - const: llcc5_base - const: llcc6_base - const: llcc7_base - const: llcc_broadcast_base - if: properties: compatible: contains: enum: - qcom,sdm845-llcc - qcom,sm8150-llcc - qcom,sm8250-llcc - qcom,sm8350-llcc then: properties: reg: items: - description: LLCC0 base register region - description: LLCC1 base register region - description: LLCC2 base register region - description: LLCC3 base register region - description: LLCC broadcast base register region reg-names: items: - const: llcc0_base - const: llcc1_base - const: llcc2_base - const: llcc3_base - const: llcc_broadcast_base - if: properties: compatible: contains: enum: - qcom,sm8450-llcc - qcom,sm8550-llcc - qcom,sm8650-llcc then: properties: reg: items: - description: LLCC0 base register region - description: LLCC1 base register region - description: LLCC2 base register region - description: LLCC3 base register region - description: LLCC broadcast OR register region - description: LLCC broadcast AND register region reg-names: items: - const: llcc0_base - const: llcc1_base - const: llcc2_base - const: llcc3_base - const: llcc_broadcast_base - const: llcc_broadcast_and_base additionalProperties: false examples: - | #include <dt-bindings/interrupt-controller/arm-gic.h> soc { #address-cells = <2>; #size-cells = <2>; system-cache-controller@1100000 { compatible = "qcom,sdm845-llcc"; reg = <0 0x01100000 0 0x50000>, <0 0x01180000 0 0x50000>, <0 0x01200000 0 0x50000>, <0 0x01280000 0 0x50000>, <0 0x01300000 0 0x50000>; reg-names = "llcc0_base", "llcc1_base", "llcc2_base", "llcc3_base", "llcc_broadcast_base"; interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; }; }; |